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31 #ifndef __CPU_O3_STORE_SET_HH__
32 #define __CPU_O3_STORE_SET_HH__
39 #include "cpu/inst_seq.hh"
40 #include "sim/host.hh"
43 bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
50 * Implements a store set predictor for determining if memory
51 * instructions are dependent upon each other. See paper "Memory
52 * Dependence Prediction using Store Sets" by Chrysos and Emer. SSID
53 * stands for Store Set ID, SSIT stands for Store Set ID Table, and
54 * LFST is Last Fetched Store Table.
59 typedef unsigned SSID;
62 /** Default constructor. init() must be called prior to use. */
65 /** Creates store set predictor with given table sizes. */
66 StoreSet(int SSIT_size, int LFST_size);
68 /** Default destructor. */
71 /** Initializes the store set predictor with the given table sizes. */
72 void init(int SSIT_size, int LFST_size);
74 /** Records a memory ordering violation between the younger load
75 * and the older store. */
76 void violation(Addr store_PC, Addr load_PC);
78 /** Inserts a load into the store set predictor. This does nothing but
79 * is included in case other predictors require a similar function.
81 void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
83 /** Inserts a store into the store set predictor. Updates the
84 * LFST if the store has a valid SSID. */
85 void insertStore(Addr store_PC, InstSeqNum store_seq_num,
88 /** Checks if the instruction with the given PC is dependent upon
89 * any store. @return Returns the sequence number of the store
90 * instruction this PC is dependent upon. Returns 0 if none.
92 InstSeqNum checkInst(Addr PC);
94 /** Records this PC/sequence number as issued. */
95 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
97 /** Squashes for a specific thread until the given sequence number. */
98 void squash(InstSeqNum squashed_num, unsigned tid);
100 /** Resets all tables. */
103 /** Debug function to dump the contents of the store list. */
107 /** Calculates the index into the SSIT based on the PC. */
108 inline int calcIndex(Addr PC)
109 { return (PC >> offsetBits) & indexMask; }
111 /** Calculates a Store Set ID based on the PC. */
112 inline SSID calcSSID(Addr PC)
113 { return ((PC ^ (PC >> 10)) % LFSTSize); }
115 /** The Store Set ID Table. */
116 std::vector<SSID> SSIT;
118 /** Bit vector to tell if the SSIT has a valid entry. */
119 std::vector<bool> validSSIT;
121 /** Last Fetched Store Table. */
122 std::vector<InstSeqNum> LFST;
124 /** Bit vector to tell if the LFST has a valid entry. */
125 std::vector<bool> validLFST;
127 /** Map of stores that have been inserted into the store set, but
128 * not yet issued or squashed.
130 std::map<InstSeqNum, int, ltseqnum> storeList;
132 typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
134 /** Store Set ID Table size, in entries. */
137 /** Last Fetched Store Table size, in entries. */
140 /** Mask to obtain the index. */
143 // HACK: Hardcoded for now.
147 #endif // __CPU_O3_STORE_SET_HH__