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31 #ifndef __CPU_O3_STORE_SET_HH__
32 #define __CPU_O3_STORE_SET_HH__
39 #include "arch/isa_traits.hh"
40 #include "cpu/inst_seq.hh"
43 bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
52 typedef unsigned SSID;
57 StoreSet(int SSIT_size, int LFST_size);
61 void init(int SSIT_size, int LFST_size);
63 void violation(Addr store_PC, Addr load_PC);
65 void insertLoad(Addr load_PC, InstSeqNum load_seq_num);
67 void insertStore(Addr store_PC, InstSeqNum store_seq_num,
70 InstSeqNum checkInst(Addr PC);
72 void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
74 void squash(InstSeqNum squashed_num, unsigned tid);
79 inline int calcIndex(Addr PC)
80 { return (PC >> offsetBits) & indexMask; }
82 inline SSID calcSSID(Addr PC)
83 { return ((PC ^ (PC >> 10)) % LFSTSize); }
85 std::vector<SSID> SSIT;
87 std::vector<bool> validSSIT;
89 std::vector<InstSeqNum> LFST;
91 std::vector<bool> validLFST;
93 std::map<InstSeqNum, int, ltseqnum> storeList;
95 typedef std::map<InstSeqNum, int, ltseqnum>::iterator SeqNumMapIt;
103 // HACK: Hardcoded for now.
107 #endif // __CPU_O3_STORE_SET_HH__