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43 #ifndef __CPU_O3_THREAD_CONTEXT_HH__
44 #define __CPU_O3_THREAD_CONTEXT_HH__
46 #include "config/the_isa.hh"
47 #include "cpu/o3/isa_specific.hh"
48 #include "cpu/thread_context.hh"
50 class EndQuiesceEvent;
56 * Derived ThreadContext class for use with the O3CPU. It
57 * provides the interface for any external objects to access a
58 * single thread's state and some general CPU state. Any time
59 * external objects try to update state through this interface,
60 * the CPU will create an event to squash all in-flight
61 * instructions in order to ensure state is maintained correctly.
62 * It must be defined specifically for the O3CPU because
63 * not all architectural state is located within the O3ThreadState
64 * (such as the commit PC, and registers), and specific actions
65 * must be taken when using this interface (such as squashing all
66 * in-flight instructions when doing a write to this interface).
69 class O3ThreadContext : public ThreadContext
72 typedef typename Impl::O3CPU O3CPU;
74 /** Pointer to the CPU. */
77 /** Pointer to the thread state that this TC corrseponds to. */
78 O3ThreadState<Impl> *thread;
80 /** Returns a pointer to the ITB. */
81 TheISA::TLB *getITBPtr() { return cpu->itb; }
83 /** Returns a pointer to the DTB. */
84 TheISA::TLB *getDTBPtr() { return cpu->dtb; }
86 CheckerCPU *getCheckerCpuPtr() { return NULL; }
91 return cpu->fetch.decoder[thread->threadId()];
94 /** Returns a pointer to this CPU. */
95 virtual BaseCPU *getCpuPtr() { return cpu; }
97 /** Reads this CPU's ID. */
98 virtual int cpuId() { return cpu->cpuId(); }
100 virtual int contextId() { return thread->contextId(); }
102 virtual void setContextId(int id) { thread->setContextId(id); }
104 /** Returns this thread's ID number. */
105 virtual int threadId() { return thread->threadId(); }
106 virtual void setThreadId(int id) { return thread->setThreadId(id); }
108 /** Returns a pointer to the system. */
109 virtual System *getSystemPtr() { return cpu->system; }
111 /** Returns a pointer to this thread's kernel statistics. */
112 virtual TheISA::Kernel::Statistics *getKernelStats()
113 { return thread->kernelStats; }
115 /** Returns a pointer to this thread's process. */
116 virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
118 virtual PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
120 virtual FSTranslatingPortProxy &getVirtProxy();
122 virtual void initMemProxies(ThreadContext *tc)
123 { thread->initMemProxies(tc); }
125 virtual SETranslatingPortProxy &getMemProxy()
126 { return thread->getMemProxy(); }
128 /** Returns this thread's status. */
129 virtual Status status() const { return thread->status(); }
131 /** Sets this thread's status. */
132 virtual void setStatus(Status new_status)
133 { thread->setStatus(new_status); }
135 /** Set the status to Active. Optional delay indicates number of
136 * cycles to wait before beginning execution. */
137 virtual void activate(Cycles delay = Cycles(1));
139 /** Set the status to Suspended. */
140 virtual void suspend(Cycles delay = Cycles(0));
142 /** Set the status to Halted. */
143 virtual void halt(Cycles delay = Cycles(0));
145 /** Dumps the function profiling information.
148 virtual void dumpFuncProfile();
150 /** Takes over execution of a thread from another CPU. */
151 virtual void takeOverFrom(ThreadContext *old_context);
153 /** Registers statistics associated with this TC. */
154 virtual void regStats(const std::string &name);
156 /** Serializes state. */
157 virtual void serialize(std::ostream &os);
158 /** Unserializes state. */
159 virtual void unserialize(Checkpoint *cp, const std::string §ion);
161 /** Reads the last tick that this thread was activated on. */
162 virtual Tick readLastActivate();
163 /** Reads the last tick that this thread was suspended on. */
164 virtual Tick readLastSuspend();
166 /** Clears the function profiling information. */
167 virtual void profileClear();
168 /** Samples the function profiling information. */
169 virtual void profileSample();
171 /** Copies the architectural registers from another TC into this TC. */
172 virtual void copyArchRegs(ThreadContext *tc);
174 /** Resets all architectural registers to 0. */
175 virtual void clearArchRegs();
177 /** Reads an integer register. */
178 virtual uint64_t readIntReg(int reg_idx);
180 virtual FloatReg readFloatReg(int reg_idx);
182 virtual FloatRegBits readFloatRegBits(int reg_idx);
184 /** Sets an integer register to a value. */
185 virtual void setIntReg(int reg_idx, uint64_t val);
187 virtual void setFloatReg(int reg_idx, FloatReg val);
189 virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
191 /** Reads this thread's PC state. */
192 virtual TheISA::PCState pcState()
193 { return cpu->pcState(thread->threadId()); }
195 /** Sets this thread's PC state. */
196 virtual void pcState(const TheISA::PCState &val);
198 virtual void pcStateNoRecord(const TheISA::PCState &val);
200 /** Reads this thread's PC. */
201 virtual Addr instAddr()
202 { return cpu->instAddr(thread->threadId()); }
204 /** Reads this thread's next PC. */
205 virtual Addr nextInstAddr()
206 { return cpu->nextInstAddr(thread->threadId()); }
208 /** Reads this thread's next PC. */
209 virtual MicroPC microPC()
210 { return cpu->microPC(thread->threadId()); }
212 /** Reads a miscellaneous register. */
213 virtual MiscReg readMiscRegNoEffect(int misc_reg)
214 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
216 /** Reads a misc. register, including any side-effects the
217 * read might have as defined by the architecture. */
218 virtual MiscReg readMiscReg(int misc_reg)
219 { return cpu->readMiscReg(misc_reg, thread->threadId()); }
221 /** Sets a misc. register. */
222 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
224 /** Sets a misc. register, including any side-effects the
225 * write might have as defined by the architecture. */
226 virtual void setMiscReg(int misc_reg, const MiscReg &val);
228 virtual int flattenIntIndex(int reg);
229 virtual int flattenFloatIndex(int reg);
231 /** Returns the number of consecutive store conditional failures. */
232 // @todo: Figure out where these store cond failures should go.
233 virtual unsigned readStCondFailures()
234 { return thread->storeCondFailures; }
236 /** Sets the number of consecutive store conditional failures. */
237 virtual void setStCondFailures(unsigned sc_failures)
238 { thread->storeCondFailures = sc_failures; }
240 // Only really makes sense for old CPU model. Lots of code
241 // outside the CPU still checks this function, so it will
242 // always return false to keep everything working.
243 /** Checks if the thread is misspeculating. Because it is
244 * very difficult to determine if the thread is
245 * misspeculating, this is set as false. */
246 virtual bool misspeculating() { return false; }
248 /** Executes a syscall in SE mode. */
249 virtual void syscall(int64_t callnum)
250 { return cpu->syscall(callnum, thread->threadId()); }
252 /** Reads the funcExeInst counter. */
253 virtual Counter readFuncExeInst() { return thread->funcExeInst; }
255 /** Returns pointer to the quiesce event. */
256 virtual EndQuiesceEvent *getQuiesceEvent()
258 return this->thread->quiesceEvent;