2 * Copyright (c) 2011-2012, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #ifndef __CPU_O3_THREAD_CONTEXT_HH__
45 #define __CPU_O3_THREAD_CONTEXT_HH__
47 #include "config/the_isa.hh"
48 #include "cpu/o3/isa_specific.hh"
49 #include "cpu/thread_context.hh"
51 class EndQuiesceEvent;
57 * Derived ThreadContext class for use with the O3CPU. It
58 * provides the interface for any external objects to access a
59 * single thread's state and some general CPU state. Any time
60 * external objects try to update state through this interface,
61 * the CPU will create an event to squash all in-flight
62 * instructions in order to ensure state is maintained correctly.
63 * It must be defined specifically for the O3CPU because
64 * not all architectural state is located within the O3ThreadState
65 * (such as the commit PC, and registers), and specific actions
66 * must be taken when using this interface (such as squashing all
67 * in-flight instructions when doing a write to this interface).
70 class O3ThreadContext : public ThreadContext
73 typedef typename Impl::O3CPU O3CPU;
75 /** Pointer to the CPU. */
78 /** Pointer to the thread state that this TC corrseponds to. */
79 O3ThreadState<Impl> *thread;
81 /** Returns a pointer to the ITB. */
82 BaseTLB *getITBPtr() override { return cpu->itb; }
84 /** Returns a pointer to the DTB. */
85 BaseTLB *getDTBPtr() override { return cpu->dtb; }
87 CheckerCPU *getCheckerCpuPtr() override { return NULL; }
92 return cpu->isa[thread->threadId()];
96 getDecoderPtr() override
98 return cpu->fetch.decoder[thread->threadId()];
101 /** Returns a pointer to this CPU. */
102 BaseCPU *getCpuPtr() override { return cpu; }
104 /** Reads this CPU's ID. */
105 int cpuId() const override { return cpu->cpuId(); }
107 /** Reads this CPU's Socket ID. */
108 uint32_t socketId() const override { return cpu->socketId(); }
110 ContextID contextId() const override { return thread->contextId(); }
112 void setContextId(ContextID id) override { thread->setContextId(id); }
114 /** Returns this thread's ID number. */
115 int threadId() const override { return thread->threadId(); }
116 void setThreadId(int id) override { return thread->setThreadId(id); }
118 /** Returns a pointer to the system. */
119 System *getSystemPtr() override { return cpu->system; }
121 /** Returns a pointer to this thread's kernel statistics. */
122 ::Kernel::Statistics *
123 getKernelStats() override
125 return thread->kernelStats;
128 /** Returns a pointer to this thread's process. */
129 Process *getProcessPtr() override { return thread->getProcessPtr(); }
131 void setProcessPtr(Process *p) override { thread->setProcessPtr(p); }
133 PortProxy &getPhysProxy() override { return thread->getPhysProxy(); }
135 PortProxy &getVirtProxy() override;
138 initMemProxies(ThreadContext *tc) override
140 thread->initMemProxies(tc);
143 /** Returns this thread's status. */
144 Status status() const override { return thread->status(); }
146 /** Sets this thread's status. */
148 setStatus(Status new_status) override
150 thread->setStatus(new_status);
153 /** Set the status to Active. */
154 void activate() override;
156 /** Set the status to Suspended. */
157 void suspend() override;
159 /** Set the status to Halted. */
160 void halt() override;
162 /** Dumps the function profiling information.
165 void dumpFuncProfile() override;
167 /** Takes over execution of a thread from another CPU. */
168 void takeOverFrom(ThreadContext *old_context) override;
170 /** Registers statistics associated with this TC. */
171 void regStats(const std::string &name) override;
173 /** Reads the last tick that this thread was activated on. */
174 Tick readLastActivate() override;
175 /** Reads the last tick that this thread was suspended on. */
176 Tick readLastSuspend() override;
178 /** Clears the function profiling information. */
179 void profileClear() override;
180 /** Samples the function profiling information. */
181 void profileSample() override;
183 /** Copies the architectural registers from another TC into this TC. */
184 void copyArchRegs(ThreadContext *tc) override;
186 /** Resets all architectural registers to 0. */
187 void clearArchRegs() override;
189 /** Reads an integer register. */
191 readReg(RegIndex reg_idx)
193 return readIntRegFlat(flattenRegId(RegId(IntRegClass,
197 readIntReg(RegIndex reg_idx) const override
199 return readIntRegFlat(flattenRegId(RegId(IntRegClass,
204 readFloatReg(RegIndex reg_idx) const override
206 return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
210 const VecRegContainer &
211 readVecReg(const RegId& id) const override
213 return readVecRegFlat(flattenRegId(id).index());
217 * Read vector register operand for modification, hierarchical indexing.
220 getWritableVecReg(const RegId& id) override
222 return getWritableVecRegFlat(flattenRegId(id).index());
225 /** Vector Register Lane Interfaces. */
227 /** Reads source vector 8bit operand. */
229 readVec8BitLaneReg(const RegId& id) const override
231 return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
235 /** Reads source vector 16bit operand. */
237 readVec16BitLaneReg(const RegId& id) const override
239 return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
243 /** Reads source vector 32bit operand. */
245 readVec32BitLaneReg(const RegId& id) const override
247 return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
251 /** Reads source vector 64bit operand. */
253 readVec64BitLaneReg(const RegId& id) const override
255 return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
259 /** Write a lane of the destination vector register. */
261 setVecLane(const RegId& reg,
262 const LaneData<LaneSize::Byte>& val) override
264 return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
267 setVecLane(const RegId& reg,
268 const LaneData<LaneSize::TwoByte>& val) override
270 return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
273 setVecLane(const RegId& reg,
274 const LaneData<LaneSize::FourByte>& val) override
276 return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
279 setVecLane(const RegId& reg,
280 const LaneData<LaneSize::EightByte>& val) override
282 return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
287 readVecElem(const RegId& reg) const override
289 return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
292 const VecPredRegContainer &
293 readVecPredReg(const RegId& id) const override
295 return readVecPredRegFlat(flattenRegId(id).index());
299 getWritableVecPredReg(const RegId& id) override
301 return getWritableVecPredRegFlat(flattenRegId(id).index());
305 readCCReg(RegIndex reg_idx) const override
307 return readCCRegFlat(flattenRegId(RegId(CCRegClass,
311 /** Sets an integer register to a value. */
313 setIntReg(RegIndex reg_idx, RegVal val) override
315 setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
319 setFloatReg(RegIndex reg_idx, RegVal val) override
321 setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
322 reg_idx)).index(), val);
326 setVecReg(const RegId& reg, const VecRegContainer& val) override
328 setVecRegFlat(flattenRegId(reg).index(), val);
332 setVecElem(const RegId& reg, const VecElem& val) override
334 setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
338 setVecPredReg(const RegId& reg,
339 const VecPredRegContainer& val) override
341 setVecPredRegFlat(flattenRegId(reg).index(), val);
345 setCCReg(RegIndex reg_idx, RegVal val) override
347 setCCRegFlat(flattenRegId(RegId(CCRegClass, reg_idx)).index(), val);
350 /** Reads this thread's PC state. */
352 pcState() const override
354 return cpu->pcState(thread->threadId());
357 /** Sets this thread's PC state. */
358 void pcState(const TheISA::PCState &val) override;
360 void pcStateNoRecord(const TheISA::PCState &val) override;
362 /** Reads this thread's PC. */
364 instAddr() const override
366 return cpu->instAddr(thread->threadId());
369 /** Reads this thread's next PC. */
371 nextInstAddr() const override
373 return cpu->nextInstAddr(thread->threadId());
376 /** Reads this thread's next PC. */
378 microPC() const override
380 return cpu->microPC(thread->threadId());
383 /** Reads a miscellaneous register. */
385 readMiscRegNoEffect(RegIndex misc_reg) const override
387 return cpu->readMiscRegNoEffect(misc_reg, thread->threadId());
390 /** Reads a misc. register, including any side-effects the
391 * read might have as defined by the architecture. */
393 readMiscReg(RegIndex misc_reg) override
395 return cpu->readMiscReg(misc_reg, thread->threadId());
398 /** Sets a misc. register. */
399 void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override;
401 /** Sets a misc. register, including any side-effects the
402 * write might have as defined by the architecture. */
403 void setMiscReg(RegIndex misc_reg, RegVal val) override;
405 RegId flattenRegId(const RegId& regId) const override;
407 /** Returns the number of consecutive store conditional failures. */
408 // @todo: Figure out where these store cond failures should go.
410 readStCondFailures() const override
412 return thread->storeCondFailures;
415 /** Sets the number of consecutive store conditional failures. */
417 setStCondFailures(unsigned sc_failures) override
419 thread->storeCondFailures = sc_failures;
422 /** Executes a syscall in SE mode. */
424 syscall(int64_t callnum, Fault *fault) override
426 return cpu->syscall(callnum, thread->threadId(), fault);
429 /** Reads the funcExeInst counter. */
430 Counter readFuncExeInst() const override { return thread->funcExeInst; }
432 /** Returns pointer to the quiesce event. */
434 getQuiesceEvent() override
436 return this->thread->quiesceEvent;
438 /** check if the cpu is currently in state update mode and squash if not.
439 * This function will return true if a trap is pending or if a fault or
440 * similar is currently writing to the thread context and doesn't want
441 * reset all the state (see noSquashFromTC).
446 if (!thread->trapPending && !thread->noSquashFromTC)
447 cpu->squashFromTC(thread->threadId());
450 RegVal readIntRegFlat(RegIndex idx) const override;
451 void setIntRegFlat(RegIndex idx, RegVal val) override;
453 RegVal readFloatRegFlat(RegIndex idx) const override;
454 void setFloatRegFlat(RegIndex idx, RegVal val) override;
456 const VecRegContainer& readVecRegFlat(RegIndex idx) const override;
457 /** Read vector register operand for modification, flat indexing. */
458 VecRegContainer& getWritableVecRegFlat(RegIndex idx) override;
459 void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override;
461 template <typename VecElem>
462 VecLaneT<VecElem, true>
463 readVecLaneFlat(RegIndex idx, int lId) const
465 return cpu->template readArchVecLane<VecElem>(idx, lId,
469 template <typename LD>
471 setVecLaneFlat(int idx, int lId, const LD& val)
473 cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
476 const VecElem &readVecElemFlat(RegIndex idx,
477 const ElemIndex& elemIndex) const override;
478 void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
479 const VecElem& val) override;
481 const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override;
482 VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) override;
483 void setVecPredRegFlat(RegIndex idx,
484 const VecPredRegContainer& val) override;
486 RegVal readCCRegFlat(RegIndex idx) const override;
487 void setCCRegFlat(RegIndex idx, RegVal val) override;