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31 #ifndef __CPU_O3_THREAD_CONTEXT_HH__
32 #define __CPU_O3_THREAD_CONTEXT_HH__
34 #include "config/the_isa.hh"
35 #include "cpu/o3/isa_specific.hh"
36 #include "cpu/thread_context.hh"
38 class EndQuiesceEvent;
43 class TranslatingPort;
46 * Derived ThreadContext class for use with the O3CPU. It
47 * provides the interface for any external objects to access a
48 * single thread's state and some general CPU state. Any time
49 * external objects try to update state through this interface,
50 * the CPU will create an event to squash all in-flight
51 * instructions in order to ensure state is maintained correctly.
52 * It must be defined specifically for the O3CPU because
53 * not all architectural state is located within the O3ThreadState
54 * (such as the commit PC, and registers), and specific actions
55 * must be taken when using this interface (such as squashing all
56 * in-flight instructions when doing a write to this interface).
59 class O3ThreadContext : public ThreadContext
62 typedef typename Impl::O3CPU O3CPU;
64 /** Pointer to the CPU. */
67 /** Pointer to the thread state that this TC corrseponds to. */
68 O3ThreadState<Impl> *thread;
70 /** Returns a pointer to the ITB. */
71 TheISA::TLB *getITBPtr() { return cpu->itb; }
73 /** Returns a pointer to the DTB. */
74 TheISA::TLB *getDTBPtr() { return cpu->dtb; }
76 Decoder *getDecoderPtr() { return &cpu->fetch.decoder; }
78 /** Returns a pointer to this CPU. */
79 virtual BaseCPU *getCpuPtr() { return cpu; }
81 /** Reads this CPU's ID. */
82 virtual int cpuId() { return cpu->cpuId(); }
84 virtual int contextId() { return thread->contextId(); }
86 virtual void setContextId(int id) { thread->setContextId(id); }
88 /** Returns this thread's ID number. */
89 virtual int threadId() { return thread->threadId(); }
90 virtual void setThreadId(int id) { return thread->setThreadId(id); }
92 /** Returns a pointer to the system. */
93 virtual System *getSystemPtr() { return cpu->system; }
96 /** Returns a pointer to this thread's kernel statistics. */
97 virtual TheISA::Kernel::Statistics *getKernelStats()
98 { return thread->kernelStats; }
100 virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
102 virtual VirtualPort *getVirtPort();
104 virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
106 virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
108 /** Returns a pointer to this thread's process. */
109 virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
111 /** Returns this thread's status. */
112 virtual Status status() const { return thread->status(); }
114 /** Sets this thread's status. */
115 virtual void setStatus(Status new_status)
116 { thread->setStatus(new_status); }
118 /** Set the status to Active. Optional delay indicates number of
119 * cycles to wait before beginning execution. */
120 virtual void activate(int delay = 1);
122 /** Set the status to Suspended. */
123 virtual void suspend(int delay = 0);
125 /** Set the status to Halted. */
126 virtual void halt(int delay = 0);
129 /** Dumps the function profiling information.
132 virtual void dumpFuncProfile();
134 /** Takes over execution of a thread from another CPU. */
135 virtual void takeOverFrom(ThreadContext *old_context);
137 /** Registers statistics associated with this TC. */
138 virtual void regStats(const std::string &name);
140 /** Serializes state. */
141 virtual void serialize(std::ostream &os);
142 /** Unserializes state. */
143 virtual void unserialize(Checkpoint *cp, const std::string §ion);
146 /** Reads the last tick that this thread was activated on. */
147 virtual Tick readLastActivate();
148 /** Reads the last tick that this thread was suspended on. */
149 virtual Tick readLastSuspend();
151 /** Clears the function profiling information. */
152 virtual void profileClear();
153 /** Samples the function profiling information. */
154 virtual void profileSample();
157 /** Copies the architectural registers from another TC into this TC. */
158 virtual void copyArchRegs(ThreadContext *tc);
160 /** Resets all architectural registers to 0. */
161 virtual void clearArchRegs();
163 /** Reads an integer register. */
164 virtual uint64_t readIntReg(int reg_idx);
166 virtual FloatReg readFloatReg(int reg_idx);
168 virtual FloatRegBits readFloatRegBits(int reg_idx);
170 /** Sets an integer register to a value. */
171 virtual void setIntReg(int reg_idx, uint64_t val);
173 virtual void setFloatReg(int reg_idx, FloatReg val);
175 virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
177 /** Reads this thread's PC state. */
178 virtual TheISA::PCState pcState()
179 { return cpu->pcState(thread->threadId()); }
181 /** Sets this thread's PC state. */
182 virtual void pcState(const TheISA::PCState &val);
184 /** Reads this thread's PC. */
185 virtual Addr instAddr()
186 { return cpu->instAddr(thread->threadId()); }
188 /** Reads this thread's next PC. */
189 virtual Addr nextInstAddr()
190 { return cpu->nextInstAddr(thread->threadId()); }
192 /** Reads this thread's next PC. */
193 virtual MicroPC microPC()
194 { return cpu->microPC(thread->threadId()); }
196 /** Reads a miscellaneous register. */
197 virtual MiscReg readMiscRegNoEffect(int misc_reg)
198 { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
200 /** Reads a misc. register, including any side-effects the
201 * read might have as defined by the architecture. */
202 virtual MiscReg readMiscReg(int misc_reg)
203 { return cpu->readMiscReg(misc_reg, thread->threadId()); }
205 /** Sets a misc. register. */
206 virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
208 /** Sets a misc. register, including any side-effects the
209 * write might have as defined by the architecture. */
210 virtual void setMiscReg(int misc_reg, const MiscReg &val);
212 virtual int flattenIntIndex(int reg);
213 virtual int flattenFloatIndex(int reg);
215 /** Returns the number of consecutive store conditional failures. */
216 // @todo: Figure out where these store cond failures should go.
217 virtual unsigned readStCondFailures()
218 { return thread->storeCondFailures; }
220 /** Sets the number of consecutive store conditional failures. */
221 virtual void setStCondFailures(unsigned sc_failures)
222 { thread->storeCondFailures = sc_failures; }
224 // Only really makes sense for old CPU model. Lots of code
225 // outside the CPU still checks this function, so it will
226 // always return false to keep everything working.
227 /** Checks if the thread is misspeculating. Because it is
228 * very difficult to determine if the thread is
229 * misspeculating, this is set as false. */
230 virtual bool misspeculating() { return false; }
233 /** Executes a syscall in SE mode. */
234 virtual void syscall(int64_t callnum)
235 { return cpu->syscall(callnum, thread->threadId()); }
237 /** Reads the funcExeInst counter. */
238 virtual Counter readFuncExeInst() { return thread->funcExeInst; }
240 /** Returns pointer to the quiesce event. */
241 virtual EndQuiesceEvent *getQuiesceEvent()
243 return this->thread->quiesceEvent;