src/cpu/o3/thread_context.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_O3_THREAD_CONTEXT_HH__
  32 #define __CPU_O3_THREAD_CONTEXT_HH__
  33
  34 #include "cpu/thread_context.hh"
  35 #include "cpu/o3/isa_specific.hh"
  36
  37 class EndQuiesceEvent;
  38 namespace Kernel {
  39     class Statistics;
  40 };
  41
  42 class TranslatingPort;
  43
  44 /**
  45  * Derived ThreadContext class for use with the O3CPU.  It
  46  * provides the interface for any external objects to access a
  47  * single thread's state and some general CPU state.  Any time
  48  * external objects try to update state through this interface,
  49  * the CPU will create an event to squash all in-flight
  50  * instructions in order to ensure state is maintained correctly.
  51  * It must be defined specifically for the O3CPU because
  52  * not all architectural state is located within the O3ThreadState
  53  * (such as the commit PC, and registers), and specific actions
  54  * must be taken when using this interface (such as squashing all
  55  * in-flight instructions when doing a write to this interface).
  56  */
  57 template <class Impl>
  58 class O3ThreadContext : public ThreadContext
  59 {
  60   public:
  61     typedef typename Impl::O3CPU O3CPU;
  62
  63    /** Pointer to the CPU. */
  64     O3CPU *cpu;
  65
  66     /** Pointer to the thread state that this TC corrseponds to. */
  67     O3ThreadState<Impl> *thread;
  68
  69     /** Returns a pointer to the ITB. */
  70     TheISA::ITB *getITBPtr() { return cpu->itb; }
  71
  72     /** Returns a pointer to the DTB. */
  73     TheISA::DTB *getDTBPtr() { return cpu->dtb; }
  74
  75     /** Returns a pointer to this CPU. */
  76     virtual BaseCPU *getCpuPtr() { return cpu; }
  77
  78     /** Sets this CPU's ID. */
  79     virtual void setCpuId(int id) { cpu->setCpuId(id); }
  80
  81     /** Reads this CPU's ID. */
  82     virtual int readCpuId() { return cpu->readCpuId(); }
  83
  84 #if FULL_SYSTEM
  85     /** Returns a pointer to the system. */
  86     virtual System *getSystemPtr() { return cpu->system; }
  87
  88     /** Returns a pointer to physical memory. */
  89     virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
  90
  91     /** Returns a pointer to this thread's kernel statistics. */
  92     virtual TheISA::Kernel::Statistics *getKernelStats()
  93     { return thread->kernelStats; }
  94
  95     virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
  96
  97     virtual VirtualPort *getVirtPort();
  98
  99     virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
 100 #else
 101     virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
 102
 103     /** Returns a pointer to this thread's process. */
 104     virtual Process *getProcessPtr() { return thread->getProcessPtr(); }
 105 #endif
 106     /** Returns this thread's status. */
 107     virtual Status status() const { return thread->status(); }
 108
 109     /** Sets this thread's status. */
 110     virtual void setStatus(Status new_status)
 111     { thread->setStatus(new_status); }
 112
 113     /** Set the status to Active.  Optional delay indicates number of
 114      * cycles to wait before beginning execution. */
 115     virtual void activate(int delay = 1);
 116
 117     /** Set the status to Suspended. */
 118     virtual void suspend(int delay = 0);
 119
 120     /** Set the status to Unallocated. */
 121     virtual void deallocate(int delay = 0);
 122
 123     /** Set the status to Halted. */
 124     virtual void halt(int delay = 0);
 125
 126 #if FULL_SYSTEM
 127     /** Dumps the function profiling information.
 128      * @todo: Implement.
 129      */
 130     virtual void dumpFuncProfile();
 131 #endif
 132     /** Takes over execution of a thread from another CPU. */
 133     virtual void takeOverFrom(ThreadContext *old_context);
 134
 135     /** Registers statistics associated with this TC. */
 136     virtual void regStats(const std::string &name);
 137
 138     /** Serializes state. */
 139     virtual void serialize(std::ostream &os);
 140     /** Unserializes state. */
 141     virtual void unserialize(Checkpoint *cp, const std::string &section);
 142
 143 #if FULL_SYSTEM
 144     /** Reads the last tick that this thread was activated on. */
 145     virtual Tick readLastActivate();
 146     /** Reads the last tick that this thread was suspended on. */
 147     virtual Tick readLastSuspend();
 148
 149     /** Clears the function profiling information. */
 150     virtual void profileClear();
 151     /** Samples the function profiling information. */
 152     virtual void profileSample();
 153 #endif
 154     /** Returns this thread's ID number. */
 155     virtual int getThreadNum() { return thread->readTid(); }
 156
 157     /** Returns the instruction this thread is currently committing.
 158      *  Only used when an instruction faults.
 159      */
 160     virtual TheISA::MachInst getInst();
 161
 162     /** Copies the architectural registers from another TC into this TC. */
 163     virtual void copyArchRegs(ThreadContext *tc);
 164
 165     /** Resets all architectural registers to 0. */
 166     virtual void clearArchRegs();
 167
 168     /** Reads an integer register. */
 169     virtual uint64_t readIntReg(int reg_idx);
 170
 171     virtual FloatReg readFloatReg(int reg_idx, int width);
 172
 173     virtual FloatReg readFloatReg(int reg_idx);
 174
 175     virtual FloatRegBits readFloatRegBits(int reg_idx, int width);
 176
 177     virtual FloatRegBits readFloatRegBits(int reg_idx);
 178
 179     /** Sets an integer register to a value. */
 180     virtual void setIntReg(int reg_idx, uint64_t val);
 181
 182     virtual void setFloatReg(int reg_idx, FloatReg val, int width);
 183
 184     virtual void setFloatReg(int reg_idx, FloatReg val);
 185
 186     virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
 187
 188     virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
 189
 190     /** Reads this thread's PC. */
 191     virtual uint64_t readPC()
 192     { return cpu->readPC(thread->readTid()); }
 193
 194     /** Sets this thread's PC. */
 195     virtual void setPC(uint64_t val);
 196
 197     /** Reads this thread's next PC. */
 198     virtual uint64_t readNextPC()
 199     { return cpu->readNextPC(thread->readTid()); }
 200
 201     /** Sets this thread's next PC. */
 202     virtual void setNextPC(uint64_t val);
 203
 204     virtual uint64_t readMicroPC()
 205     { return cpu->readMicroPC(thread->readTid()); }
 206
 207     virtual void setMicroPC(uint64_t val);
 208
 209     virtual uint64_t readNextMicroPC()
 210     { return cpu->readNextMicroPC(thread->readTid()); }
 211
 212     virtual void setNextMicroPC(uint64_t val);
 213
 214     /** Reads a miscellaneous register. */
 215     virtual MiscReg readMiscRegNoEffect(int misc_reg)
 216     { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
 217
 218     /** Reads a misc. register, including any side-effects the
 219      * read might have as defined by the architecture. */
 220     virtual MiscReg readMiscReg(int misc_reg)
 221     { return cpu->readMiscReg(misc_reg, thread->readTid()); }
 222
 223     /** Sets a misc. register. */
 224     virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 225
 226     /** Sets a misc. register, including any side-effects the
 227      * write might have as defined by the architecture. */
 228     virtual void setMiscReg(int misc_reg, const MiscReg &val);
 229
 230     /** Returns the number of consecutive store conditional failures. */
 231     // @todo: Figure out where these store cond failures should go.
 232     virtual unsigned readStCondFailures()
 233     { return thread->storeCondFailures; }
 234
 235     /** Sets the number of consecutive store conditional failures. */
 236     virtual void setStCondFailures(unsigned sc_failures)
 237     { thread->storeCondFailures = sc_failures; }
 238
 239     // Only really makes sense for old CPU model.  Lots of code
 240     // outside the CPU still checks this function, so it will
 241     // always return false to keep everything working.
 242     /** Checks if the thread is misspeculating.  Because it is
 243      * very difficult to determine if the thread is
 244      * misspeculating, this is set as false. */
 245     virtual bool misspeculating() { return false; }
 246
 247 #if !FULL_SYSTEM
 248     /** Gets a syscall argument by index. */
 249     virtual IntReg getSyscallArg(int i);
 250
 251     /** Sets a syscall argument. */
 252     virtual void setSyscallArg(int i, IntReg val);
 253
 254     /** Sets the syscall return value. */
 255     virtual void setSyscallReturn(SyscallReturn return_value);
 256
 257     /** Executes a syscall in SE mode. */
 258     virtual void syscall(int64_t callnum)
 259     { return cpu->syscall(callnum, thread->readTid()); }
 260
 261     /** Reads the funcExeInst counter. */
 262     virtual Counter readFuncExeInst() { return thread->funcExeInst; }
 263 #else
 264     /** Returns pointer to the quiesce event. */
 265     virtual EndQuiesceEvent *getQuiesceEvent()
 266     {
 267         return this->thread->quiesceEvent;
 268     }
 269 #endif
 270
 271     virtual uint64_t readNextNPC()
 272     {
 273         return this->cpu->readNextNPC(this->thread->readTid());
 274     }
 275
 276     virtual void setNextNPC(uint64_t val)
 277     {
 278 #if THE_ISA == ALPHA_ISA
 279         panic("Not supported on Alpha!");
 280 #endif
 281         this->cpu->setNextNPC(val, this->thread->readTid());
 282     }
 283
 284     /** This function exits the thread context in the CPU and returns
 285      * 1 if the CPU has no more active threads (meaning it's OK to exit);
 286      * Used in syscall-emulation mode when a thread executes the 'exit'
 287      * syscall.
 288      */
 289     virtual int exit()
 290     {
 291         this->deallocate();
 292
 293         // If there are still threads executing in the system
 294         if (this->cpu->numActiveThreads())
 295             return 0; // don't exit simulation
 296         else
 297             return 1; // exit simulation
 298     }
 299 };
 300
 301 #endif