src/cpu/o3/thread_context_impl.hh

   1 /*
   2  * Copyright (c) 2010-2012, 2016-2017 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
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   9  * to a hardware implementation of the functionality of the software
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  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  16  * All rights reserved.
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  19  * modification, are permitted provided that the following conditions are
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  27  * this software without specific prior written permission.
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  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Kevin Lim
  42  *          Korey Sewell
  43  */
  44
  45 #ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
  46 #define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
  47
  48 #include "arch/generic/traits.hh"
  49 #include "arch/kernel_stats.hh"
  50 #include "arch/registers.hh"
  51 #include "config/the_isa.hh"
  52 #include "cpu/o3/thread_context.hh"
  53 #include "cpu/quiesce_event.hh"
  54 #include "debug/O3CPU.hh"
  55
  56 template <class Impl>
  57 FSTranslatingPortProxy&
  58 O3ThreadContext<Impl>::getVirtProxy()
  59 {
  60     return thread->getVirtProxy();
  61 }
  62
  63 template <class Impl>
  64 void
  65 O3ThreadContext<Impl>::dumpFuncProfile()
  66 {
  67     thread->dumpFuncProfile();
  68 }
  69
  70 template <class Impl>
  71 void
  72 O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
  73 {
  74     ::takeOverFrom(*this, *old_context);
  75     TheISA::Decoder *newDecoder = getDecoderPtr();
  76     TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
  77     newDecoder->takeOverFrom(oldDecoder);
  78
  79     thread->kernelStats = old_context->getKernelStats();
  80     thread->funcExeInst = old_context->readFuncExeInst();
  81
  82     thread->noSquashFromTC = false;
  83     thread->trapPending = false;
  84 }
  85
  86 template <class Impl>
  87 void
  88 O3ThreadContext<Impl>::activate()
  89 {
  90     DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
  91             threadId());
  92
  93     if (thread->status() == ThreadContext::Active)
  94         return;
  95
  96     thread->lastActivate = curTick();
  97     thread->setStatus(ThreadContext::Active);
  98
  99     // status() == Suspended
 100     cpu->activateContext(thread->threadId());
 101 }
 102
 103 template <class Impl>
 104 void
 105 O3ThreadContext<Impl>::suspend()
 106 {
 107     DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
 108             threadId());
 109
 110     if (thread->status() == ThreadContext::Suspended)
 111         return;
 112
 113     if (cpu->isDraining()) {
 114         DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
 115         return;
 116     }
 117
 118     thread->lastActivate = curTick();
 119     thread->lastSuspend = curTick();
 120
 121     thread->setStatus(ThreadContext::Suspended);
 122     cpu->suspendContext(thread->threadId());
 123 }
 124
 125 template <class Impl>
 126 void
 127 O3ThreadContext<Impl>::halt()
 128 {
 129     DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
 130
 131     if (thread->status() == ThreadContext::Halting ||
 132         thread->status() == ThreadContext::Halted)
 133         return;
 134
 135     // the thread is not going to halt/terminate immediately in this cycle.
 136     // The thread will be removed after an exit trap is processed
 137     // (e.g., after trapLatency cycles). Until then, the thread's status
 138     // will be Halting.
 139     thread->setStatus(ThreadContext::Halting);
 140
 141     // add this thread to the exiting list to mark that it is trying to exit.
 142     cpu->addThreadToExitingList(thread->threadId());
 143 }
 144
 145 template <class Impl>
 146 void
 147 O3ThreadContext<Impl>::regStats(const std::string &name)
 148 {
 149     if (FullSystem) {
 150         thread->kernelStats = new TheISA::Kernel::Statistics();
 151         thread->kernelStats->regStats(name + ".kern");
 152     }
 153 }
 154
 155 template <class Impl>
 156 Tick
 157 O3ThreadContext<Impl>::readLastActivate()
 158 {
 159     return thread->lastActivate;
 160 }
 161
 162 template <class Impl>
 163 Tick
 164 O3ThreadContext<Impl>::readLastSuspend()
 165 {
 166     return thread->lastSuspend;
 167 }
 168
 169 template <class Impl>
 170 void
 171 O3ThreadContext<Impl>::profileClear()
 172 {
 173     thread->profileClear();
 174 }
 175
 176 template <class Impl>
 177 void
 178 O3ThreadContext<Impl>::profileSample()
 179 {
 180     thread->profileSample();
 181 }
 182
 183 template <class Impl>
 184 void
 185 O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
 186 {
 187     // Set vector renaming mode before copying registers
 188     cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));
 189
 190     // Prevent squashing
 191     thread->noSquashFromTC = true;
 192     TheISA::copyRegs(tc, this);
 193     thread->noSquashFromTC = false;
 194
 195     if (!FullSystem)
 196         this->thread->funcExeInst = tc->readFuncExeInst();
 197 }
 198
 199 template <class Impl>
 200 void
 201 O3ThreadContext<Impl>::clearArchRegs()
 202 {
 203     cpu->isa[thread->threadId()]->clear();
 204 }
 205
 206 template <class Impl>
 207 RegVal
 208 O3ThreadContext<Impl>::readIntRegFlat(int reg_idx)
 209 {
 210     return cpu->readArchIntReg(reg_idx, thread->threadId());
 211 }
 212
 213 template <class Impl>
 214 RegVal
 215 O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
 216 {
 217     return cpu->readArchFloatReg(reg_idx, thread->threadId());
 218 }
 219
 220 template <class Impl>
 221 const TheISA::VecRegContainer&
 222 O3ThreadContext<Impl>::readVecRegFlat(int reg_id) const
 223 {
 224     return cpu->readArchVecReg(reg_id, thread->threadId());
 225 }
 226
 227 template <class Impl>
 228 TheISA::VecRegContainer&
 229 O3ThreadContext<Impl>::getWritableVecRegFlat(int reg_id)
 230 {
 231     return cpu->getWritableArchVecReg(reg_id, thread->threadId());
 232 }
 233
 234 template <class Impl>
 235 const TheISA::VecElem&
 236 O3ThreadContext<Impl>::readVecElemFlat(const RegIndex& idx,
 237                                            const ElemIndex& elemIndex) const
 238 {
 239     return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
 240 }
 241
 242 template <class Impl>
 243 const TheISA::VecPredRegContainer&
 244 O3ThreadContext<Impl>::readVecPredRegFlat(int reg_id) const
 245 {
 246     return cpu->readArchVecPredReg(reg_id, thread->threadId());
 247 }
 248
 249 template <class Impl>
 250 TheISA::VecPredRegContainer&
 251 O3ThreadContext<Impl>::getWritableVecPredRegFlat(int reg_id)
 252 {
 253     return cpu->getWritableArchVecPredReg(reg_id, thread->threadId());
 254 }
 255
 256 template <class Impl>
 257 RegVal
 258 O3ThreadContext<Impl>::readCCRegFlat(int reg_idx)
 259 {
 260     return cpu->readArchCCReg(reg_idx, thread->threadId());
 261 }
 262
 263 template <class Impl>
 264 void
 265 O3ThreadContext<Impl>::setIntRegFlat(int reg_idx, RegVal val)
 266 {
 267     cpu->setArchIntReg(reg_idx, val, thread->threadId());
 268
 269     conditionalSquash();
 270 }
 271
 272 template <class Impl>
 273 void
 274 O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, RegVal val)
 275 {
 276     cpu->setArchFloatReg(reg_idx, val, thread->threadId());
 277
 278     conditionalSquash();
 279 }
 280
 281 template <class Impl>
 282 void
 283 O3ThreadContext<Impl>::setVecRegFlat(int reg_idx, const VecRegContainer& val)
 284 {
 285     cpu->setArchVecReg(reg_idx, val, thread->threadId());
 286
 287     conditionalSquash();
 288 }
 289
 290 template <class Impl>
 291 void
 292 O3ThreadContext<Impl>::setVecElemFlat(const RegIndex& idx,
 293         const ElemIndex& elemIndex, const VecElem& val)
 294 {
 295     cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
 296     conditionalSquash();
 297 }
 298
 299 template <class Impl>
 300 void
 301 O3ThreadContext<Impl>::setVecPredRegFlat(int reg_idx,
 302                                          const VecPredRegContainer& val)
 303 {
 304     cpu->setArchVecPredReg(reg_idx, val, thread->threadId());
 305
 306     conditionalSquash();
 307 }
 308
 309 template <class Impl>
 310 void
 311 O3ThreadContext<Impl>::setCCRegFlat(int reg_idx, RegVal val)
 312 {
 313     cpu->setArchCCReg(reg_idx, val, thread->threadId());
 314
 315     conditionalSquash();
 316 }
 317
 318 template <class Impl>
 319 void
 320 O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
 321 {
 322     cpu->pcState(val, thread->threadId());
 323
 324     conditionalSquash();
 325 }
 326
 327 template <class Impl>
 328 void
 329 O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
 330 {
 331     cpu->pcState(val, thread->threadId());
 332
 333     conditionalSquash();
 334 }
 335
 336 template <class Impl>
 337 RegId
 338 O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
 339 {
 340     return cpu->isa[thread->threadId()]->flattenRegId(regId);
 341 }
 342
 343 template <class Impl>
 344 void
 345 O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val)
 346 {
 347     cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
 348
 349     conditionalSquash();
 350 }
 351
 352 #endif//__CPU_O3_THREAD_CONTEXT_IMPL_HH__
 353 template <class Impl>
 354 void
 355 O3ThreadContext<Impl>::setMiscReg(int misc_reg, RegVal val)
 356 {
 357     cpu->setMiscReg(misc_reg, val, thread->threadId());
 358
 359     conditionalSquash();
 360 }
 361