2 * Copyright (c) 2010-2012, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
43 #define __CPU_O3_THREAD_CONTEXT_IMPL_HH__
45 #include "arch/generic/traits.hh"
46 #include "arch/kernel_stats.hh"
47 #include "arch/registers.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/o3/thread_context.hh"
50 #include "cpu/quiesce_event.hh"
51 #include "debug/O3CPU.hh"
55 O3ThreadContext<Impl>::getVirtProxy()
57 return thread->getVirtProxy();
62 O3ThreadContext<Impl>::dumpFuncProfile()
64 thread->dumpFuncProfile();
69 O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
71 ::takeOverFrom(*this, *old_context);
72 TheISA::Decoder *newDecoder = getDecoderPtr();
73 TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
74 newDecoder->takeOverFrom(oldDecoder);
76 thread->kernelStats = old_context->getKernelStats();
77 thread->funcExeInst = old_context->readFuncExeInst();
79 thread->noSquashFromTC = false;
80 thread->trapPending = false;
85 O3ThreadContext<Impl>::activate()
87 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
90 if (thread->status() == ThreadContext::Active)
93 thread->lastActivate = curTick();
94 thread->setStatus(ThreadContext::Active);
96 // status() == Suspended
97 cpu->activateContext(thread->threadId());
100 template <class Impl>
102 O3ThreadContext<Impl>::suspend()
104 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
107 if (thread->status() == ThreadContext::Suspended)
110 if (cpu->isDraining()) {
111 DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
115 thread->lastActivate = curTick();
116 thread->lastSuspend = curTick();
118 thread->setStatus(ThreadContext::Suspended);
119 cpu->suspendContext(thread->threadId());
122 template <class Impl>
124 O3ThreadContext<Impl>::halt()
126 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
128 if (thread->status() == ThreadContext::Halting ||
129 thread->status() == ThreadContext::Halted)
132 // the thread is not going to halt/terminate immediately in this cycle.
133 // The thread will be removed after an exit trap is processed
134 // (e.g., after trapLatency cycles). Until then, the thread's status
136 thread->setStatus(ThreadContext::Halting);
138 // add this thread to the exiting list to mark that it is trying to exit.
139 cpu->addThreadToExitingList(thread->threadId());
142 template <class Impl>
144 O3ThreadContext<Impl>::regStats(const std::string &name)
147 thread->kernelStats = new TheISA::Kernel::Statistics();
148 thread->kernelStats->regStats(name + ".kern");
152 template <class Impl>
154 O3ThreadContext<Impl>::readLastActivate()
156 return thread->lastActivate;
159 template <class Impl>
161 O3ThreadContext<Impl>::readLastSuspend()
163 return thread->lastSuspend;
166 template <class Impl>
168 O3ThreadContext<Impl>::profileClear()
170 thread->profileClear();
173 template <class Impl>
175 O3ThreadContext<Impl>::profileSample()
177 thread->profileSample();
180 template <class Impl>
182 O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
184 // Set vector renaming mode before copying registers
185 cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));
188 thread->noSquashFromTC = true;
189 TheISA::copyRegs(tc, this);
190 thread->noSquashFromTC = false;
193 this->thread->funcExeInst = tc->readFuncExeInst();
196 template <class Impl>
198 O3ThreadContext<Impl>::clearArchRegs()
200 cpu->isa[thread->threadId()]->clear();
203 template <class Impl>
205 O3ThreadContext<Impl>::readIntRegFlat(RegIndex reg_idx) const
207 return cpu->readArchIntReg(reg_idx, thread->threadId());
210 template <class Impl>
212 O3ThreadContext<Impl>::readFloatRegFlat(RegIndex reg_idx) const
214 return cpu->readArchFloatReg(reg_idx, thread->threadId());
217 template <class Impl>
218 const TheISA::VecRegContainer&
219 O3ThreadContext<Impl>::readVecRegFlat(RegIndex reg_id) const
221 return cpu->readArchVecReg(reg_id, thread->threadId());
224 template <class Impl>
225 TheISA::VecRegContainer&
226 O3ThreadContext<Impl>::getWritableVecRegFlat(RegIndex reg_id)
228 return cpu->getWritableArchVecReg(reg_id, thread->threadId());
231 template <class Impl>
232 const TheISA::VecElem&
233 O3ThreadContext<Impl>::readVecElemFlat(RegIndex idx,
234 const ElemIndex& elemIndex) const
236 return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
239 template <class Impl>
240 const TheISA::VecPredRegContainer&
241 O3ThreadContext<Impl>::readVecPredRegFlat(RegIndex reg_id) const
243 return cpu->readArchVecPredReg(reg_id, thread->threadId());
246 template <class Impl>
247 TheISA::VecPredRegContainer&
248 O3ThreadContext<Impl>::getWritableVecPredRegFlat(RegIndex reg_id)
250 return cpu->getWritableArchVecPredReg(reg_id, thread->threadId());
253 template <class Impl>
255 O3ThreadContext<Impl>::readCCRegFlat(RegIndex reg_idx) const
257 return cpu->readArchCCReg(reg_idx, thread->threadId());
260 template <class Impl>
262 O3ThreadContext<Impl>::setIntRegFlat(RegIndex reg_idx, RegVal val)
264 cpu->setArchIntReg(reg_idx, val, thread->threadId());
269 template <class Impl>
271 O3ThreadContext<Impl>::setFloatRegFlat(RegIndex reg_idx, RegVal val)
273 cpu->setArchFloatReg(reg_idx, val, thread->threadId());
278 template <class Impl>
280 O3ThreadContext<Impl>::setVecRegFlat(
281 RegIndex reg_idx, const VecRegContainer& val)
283 cpu->setArchVecReg(reg_idx, val, thread->threadId());
288 template <class Impl>
290 O3ThreadContext<Impl>::setVecElemFlat(RegIndex idx,
291 const ElemIndex& elemIndex, const VecElem& val)
293 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
297 template <class Impl>
299 O3ThreadContext<Impl>::setVecPredRegFlat(RegIndex reg_idx,
300 const VecPredRegContainer& val)
302 cpu->setArchVecPredReg(reg_idx, val, thread->threadId());
307 template <class Impl>
309 O3ThreadContext<Impl>::setCCRegFlat(RegIndex reg_idx, RegVal val)
311 cpu->setArchCCReg(reg_idx, val, thread->threadId());
316 template <class Impl>
318 O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
320 cpu->pcState(val, thread->threadId());
325 template <class Impl>
327 O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
329 cpu->pcState(val, thread->threadId());
334 template <class Impl>
336 O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
338 return cpu->isa[thread->threadId()]->flattenRegId(regId);
341 template <class Impl>
343 O3ThreadContext<Impl>::setMiscRegNoEffect(RegIndex misc_reg, RegVal val)
345 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
350 template <class Impl>
352 O3ThreadContext<Impl>::setMiscReg(RegIndex misc_reg, RegVal val)
354 cpu->setMiscReg(misc_reg, val, thread->threadId());
359 #endif //__CPU_O3_THREAD_CONTEXT_IMPL_HH__