src/cpu/o3/thread_context_impl.hh

   1 /*
   2  * Copyright (c) 2010-2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Korey Sewell
  42  */
  43
  44 #include "arch/kernel_stats.hh"
  45 #include "arch/registers.hh"
  46 #include "config/the_isa.hh"
  47 #include "cpu/o3/thread_context.hh"
  48 #include "cpu/quiesce_event.hh"
  49 #include "debug/O3CPU.hh"
  50
  51 template <class Impl>
  52 FSTranslatingPortProxy&
  53 O3ThreadContext<Impl>::getVirtProxy()
  54 {
  55     return thread->getVirtProxy();
  56 }
  57
  58 template <class Impl>
  59 void
  60 O3ThreadContext<Impl>::dumpFuncProfile()
  61 {
  62     thread->dumpFuncProfile();
  63 }
  64
  65 template <class Impl>
  66 void
  67 O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
  68 {
  69     // some things should already be set up
  70     assert(getSystemPtr() == old_context->getSystemPtr());
  71     assert(getProcessPtr() == old_context->getProcessPtr());
  72
  73     // copy over functional state
  74     setStatus(old_context->status());
  75     copyArchRegs(old_context);
  76     setContextId(old_context->contextId());
  77     setThreadId(old_context->threadId());
  78
  79     if (FullSystem) {
  80         EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
  81         if (other_quiesce) {
  82             // Point the quiesce event's TC at this TC so that it wakes up
  83             // the proper CPU.
  84             other_quiesce->tc = this;
  85         }
  86         if (thread->quiesceEvent) {
  87             thread->quiesceEvent->tc = this;
  88         }
  89
  90         // Transfer kernel stats from one CPU to the other.
  91         thread->kernelStats = old_context->getKernelStats();
  92         cpu->lockFlag = false;
  93     } else {
  94         thread->funcExeInst = old_context->readFuncExeInst();
  95     }
  96
  97     old_context->setStatus(ThreadContext::Halted);
  98
  99     thread->inSyscall = false;
 100     thread->trapPending = false;
 101 }
 102
 103 template <class Impl>
 104 void
 105 O3ThreadContext<Impl>::activate(Cycles delay)
 106 {
 107     DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
 108             threadId());
 109
 110     if (thread->status() == ThreadContext::Active)
 111         return;
 112
 113     thread->lastActivate = curTick();
 114     thread->setStatus(ThreadContext::Active);
 115
 116     // status() == Suspended
 117     cpu->activateContext(thread->threadId(), delay);
 118 }
 119
 120 template <class Impl>
 121 void
 122 O3ThreadContext<Impl>::suspend(Cycles delay)
 123 {
 124     DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
 125             threadId());
 126
 127     if (thread->status() == ThreadContext::Suspended)
 128         return;
 129
 130     thread->lastActivate = curTick();
 131     thread->lastSuspend = curTick();
 132
 133     thread->setStatus(ThreadContext::Suspended);
 134     cpu->suspendContext(thread->threadId());
 135 }
 136
 137 template <class Impl>
 138 void
 139 O3ThreadContext<Impl>::halt(Cycles delay)
 140 {
 141     DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
 142             threadId());
 143
 144     if (thread->status() == ThreadContext::Halted)
 145         return;
 146
 147     thread->setStatus(ThreadContext::Halted);
 148     cpu->haltContext(thread->threadId());
 149 }
 150
 151 template <class Impl>
 152 void
 153 O3ThreadContext<Impl>::regStats(const std::string &name)
 154 {
 155     if (FullSystem) {
 156         thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
 157         thread->kernelStats->regStats(name + ".kern");
 158     }
 159 }
 160
 161 template <class Impl>
 162 void
 163 O3ThreadContext<Impl>::serialize(std::ostream &os)
 164 {
 165     if (FullSystem && thread->kernelStats)
 166         thread->kernelStats->serialize(os);
 167 }
 168
 169 template <class Impl>
 170 void
 171 O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string &section)
 172 {
 173     if (FullSystem && thread->kernelStats)
 174         thread->kernelStats->unserialize(cp, section);
 175 }
 176
 177 template <class Impl>
 178 Tick
 179 O3ThreadContext<Impl>::readLastActivate()
 180 {
 181     return thread->lastActivate;
 182 }
 183
 184 template <class Impl>
 185 Tick
 186 O3ThreadContext<Impl>::readLastSuspend()
 187 {
 188     return thread->lastSuspend;
 189 }
 190
 191 template <class Impl>
 192 void
 193 O3ThreadContext<Impl>::profileClear()
 194 {
 195     thread->profileClear();
 196 }
 197
 198 template <class Impl>
 199 void
 200 O3ThreadContext<Impl>::profileSample()
 201 {
 202     thread->profileSample();
 203 }
 204
 205 template <class Impl>
 206 void
 207 O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
 208 {
 209     // Prevent squashing
 210     thread->inSyscall = true;
 211     TheISA::copyRegs(tc, this);
 212     thread->inSyscall = false;
 213
 214     if (!FullSystem)
 215         this->thread->funcExeInst = tc->readFuncExeInst();
 216 }
 217
 218 template <class Impl>
 219 void
 220 O3ThreadContext<Impl>::clearArchRegs()
 221 {
 222     cpu->isa[thread->threadId()].clear();
 223 }
 224
 225 template <class Impl>
 226 uint64_t
 227 O3ThreadContext<Impl>::readIntReg(int reg_idx)
 228 {
 229     reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
 230     return cpu->readArchIntReg(reg_idx, thread->threadId());
 231 }
 232
 233 template <class Impl>
 234 TheISA::FloatReg
 235 O3ThreadContext<Impl>::readFloatReg(int reg_idx)
 236 {
 237     reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
 238     return cpu->readArchFloatReg(reg_idx, thread->threadId());
 239 }
 240
 241 template <class Impl>
 242 TheISA::FloatRegBits
 243 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
 244 {
 245     reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
 246     return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
 247 }
 248
 249 template <class Impl>
 250 void
 251 O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
 252 {
 253     reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
 254     cpu->setArchIntReg(reg_idx, val, thread->threadId());
 255
 256     // Squash if we're not already in a state update mode.
 257     if (!thread->trapPending && !thread->inSyscall) {
 258         cpu->squashFromTC(thread->threadId());
 259     }
 260 }
 261
 262 template <class Impl>
 263 void
 264 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
 265 {
 266     reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
 267     cpu->setArchFloatReg(reg_idx, val, thread->threadId());
 268
 269     if (!thread->trapPending && !thread->inSyscall) {
 270         cpu->squashFromTC(thread->threadId());
 271     }
 272 }
 273
 274 template <class Impl>
 275 void
 276 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
 277 {
 278     reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
 279     cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
 280
 281     // Squash if we're not already in a state update mode.
 282     if (!thread->trapPending && !thread->inSyscall) {
 283         cpu->squashFromTC(thread->threadId());
 284     }
 285 }
 286
 287 template <class Impl>
 288 void
 289 O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
 290 {
 291     cpu->pcState(val, thread->threadId());
 292
 293     // Squash if we're not already in a state update mode.
 294     if (!thread->trapPending && !thread->inSyscall) {
 295         cpu->squashFromTC(thread->threadId());
 296     }
 297 }
 298
 299 template <class Impl>
 300 void
 301 O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
 302 {
 303     cpu->pcState(val, thread->threadId());
 304
 305     // Squash if we're not already in a state update mode.
 306     if (!thread->trapPending && !thread->inSyscall) {
 307         cpu->squashFromTC(thread->threadId());
 308     }
 309 }
 310
 311 template <class Impl>
 312 int
 313 O3ThreadContext<Impl>::flattenIntIndex(int reg)
 314 {
 315     return cpu->isa[thread->threadId()].flattenIntIndex(reg);
 316 }
 317
 318 template <class Impl>
 319 int
 320 O3ThreadContext<Impl>::flattenFloatIndex(int reg)
 321 {
 322     return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
 323 }
 324
 325 template <class Impl>
 326 void
 327 O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 328 {
 329     cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
 330
 331     // Squash if we're not already in a state update mode.
 332     if (!thread->trapPending && !thread->inSyscall) {
 333         cpu->squashFromTC(thread->threadId());
 334     }
 335 }
 336
 337 template <class Impl>
 338 void
 339 O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
 340 {
 341     cpu->setMiscReg(misc_reg, val, thread->threadId());
 342
 343     // Squash if we're not already in a state update mode.
 344     if (!thread->trapPending && !thread->inSyscall) {
 345         cpu->squashFromTC(thread->threadId());
 346     }
 347 }
 348