2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "cpu/o3/thread_context.hh"
33 #include "cpu/quiesce_event.hh"
35 using namespace TheISA;
40 O3ThreadContext<Impl>::getVirtPort(ThreadContext *src_tc)
43 return thread->getVirtPort();
48 vp = new VirtualPort("tc-vport", src_tc);
49 mem_port = cpu->system->physmem->getPort("functional");
50 mem_port->setPeer(vp);
51 vp->setPeer(mem_port);
57 O3ThreadContext<Impl>::dumpFuncProfile()
59 // Currently not supported
65 O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
67 // some things should already be set up
69 assert(getSystemPtr() == old_context->getSystemPtr());
71 assert(getProcessPtr() == old_context->getProcessPtr());
74 // copy over functional state
75 setStatus(old_context->status());
76 copyArchRegs(old_context);
77 setCpuId(old_context->readCpuId());
80 thread->funcExeInst = old_context->readFuncExeInst();
82 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
84 // Point the quiesce event's TC at this TC so that it wakes up
86 other_quiesce->tc = this;
88 if (thread->quiesceEvent) {
89 thread->quiesceEvent->tc = this;
92 // Transfer kernel stats from one CPU to the other.
93 thread->kernelStats = old_context->getKernelStats();
94 // storeCondFailures = 0;
95 cpu->lockFlag = false;
98 old_context->setStatus(ThreadContext::Unallocated);
100 thread->inSyscall = false;
101 thread->trapPending = false;
105 template <class Impl>
107 O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp)
109 delete vp->getPeer();
114 template <class Impl>
116 O3ThreadContext<Impl>::activate(int delay)
118 DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
121 if (thread->status() == ThreadContext::Active)
125 thread->lastActivate = curTick;
128 if (thread->status() == ThreadContext::Unallocated) {
129 cpu->activateWhenReady(thread->readTid());
133 thread->setStatus(ThreadContext::Active);
135 // status() == Suspended
136 cpu->activateContext(thread->readTid(), delay);
139 template <class Impl>
141 O3ThreadContext<Impl>::suspend()
143 DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
146 if (thread->status() == ThreadContext::Suspended)
150 thread->lastActivate = curTick;
151 thread->lastSuspend = curTick;
155 // Don't change the status from active if there are pending interrupts
156 if (cpu->check_interrupts()) {
157 assert(status() == ThreadContext::Active);
162 thread->setStatus(ThreadContext::Suspended);
163 cpu->suspendContext(thread->readTid());
166 template <class Impl>
168 O3ThreadContext<Impl>::deallocate(int delay)
170 DPRINTF(O3CPU, "Calling deallocate on Thread Context %d\n",
173 if (thread->status() == ThreadContext::Unallocated)
176 thread->setStatus(ThreadContext::Unallocated);
177 cpu->deallocateContext(thread->readTid(), delay);
180 template <class Impl>
182 O3ThreadContext<Impl>::halt()
184 DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
187 if (thread->status() == ThreadContext::Halted)
190 thread->setStatus(ThreadContext::Halted);
191 cpu->haltContext(thread->readTid());
194 template <class Impl>
196 O3ThreadContext<Impl>::regStats(const std::string &name)
199 thread->kernelStats = new Kernel::Statistics(cpu->system);
200 thread->kernelStats->regStats(name + ".kern");
204 template <class Impl>
206 O3ThreadContext<Impl>::serialize(std::ostream &os)
209 if (thread->kernelStats)
210 thread->kernelStats->serialize(os);
215 template <class Impl>
217 O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
220 if (thread->kernelStats)
221 thread->kernelStats->unserialize(cp, section);
227 template <class Impl>
229 O3ThreadContext<Impl>::readLastActivate()
231 return thread->lastActivate;
234 template <class Impl>
236 O3ThreadContext<Impl>::readLastSuspend()
238 return thread->lastSuspend;
241 template <class Impl>
243 O3ThreadContext<Impl>::profileClear()
246 template <class Impl>
248 O3ThreadContext<Impl>::profileSample()
252 template <class Impl>
254 O3ThreadContext<Impl>:: getInst()
256 return thread->getInst();
259 template <class Impl>
261 O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
263 // This function will mess things up unless the ROB is empty and
264 // there are no instructions in the pipeline.
265 unsigned tid = thread->readTid();
266 PhysRegIndex renamed_reg;
268 // First loop through the integer registers.
269 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
270 renamed_reg = cpu->renameMap[tid].lookup(i);
272 DPRINTF(O3CPU, "Copying over register %i, had data %lli, "
273 "now has data %lli.\n",
274 renamed_reg, cpu->readIntReg(renamed_reg),
277 cpu->setIntReg(renamed_reg, tc->readIntReg(i));
280 // Then loop through the floating point registers.
281 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
282 renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag);
283 cpu->setFloatRegBits(renamed_reg,
284 tc->readFloatRegBits(i));
287 // Copy the misc regs.
288 copyMiscRegs(tc, this);
290 // Then finally set the PC and the next PC.
291 cpu->setPC(tc->readPC(), tid);
292 cpu->setNextPC(tc->readNextPC(), tid);
294 this->thread->funcExeInst = tc->readFuncExeInst();
298 template <class Impl>
300 O3ThreadContext<Impl>::clearArchRegs()
303 template <class Impl>
305 O3ThreadContext<Impl>::readIntReg(int reg_idx)
307 return cpu->readArchIntReg(reg_idx, thread->readTid());
310 template <class Impl>
312 O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
316 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
318 return cpu->readArchFloatRegDouble(reg_idx, thread->readTid());
320 panic("Unsupported width!");
325 template <class Impl>
327 O3ThreadContext<Impl>::readFloatReg(int reg_idx)
329 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
332 template <class Impl>
334 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
336 DPRINTF(Fault, "Reading floatint register through the TC!\n");
337 return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
340 template <class Impl>
342 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
344 return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
347 template <class Impl>
349 O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
351 cpu->setArchIntReg(reg_idx, val, thread->readTid());
353 // Squash if we're not already in a state update mode.
354 if (!thread->trapPending && !thread->inSyscall) {
355 cpu->squashFromTC(thread->readTid());
359 template <class Impl>
361 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
365 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
368 cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid());
372 // Squash if we're not already in a state update mode.
373 if (!thread->trapPending && !thread->inSyscall) {
374 cpu->squashFromTC(thread->readTid());
378 template <class Impl>
380 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
382 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
384 if (!thread->trapPending && !thread->inSyscall) {
385 cpu->squashFromTC(thread->readTid());
389 template <class Impl>
391 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
394 DPRINTF(Fault, "Setting floatint register through the TC!\n");
395 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
397 // Squash if we're not already in a state update mode.
398 if (!thread->trapPending && !thread->inSyscall) {
399 cpu->squashFromTC(thread->readTid());
403 template <class Impl>
405 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
407 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
409 // Squash if we're not already in a state update mode.
410 if (!thread->trapPending && !thread->inSyscall) {
411 cpu->squashFromTC(thread->readTid());
415 template <class Impl>
417 O3ThreadContext<Impl>::setPC(uint64_t val)
419 cpu->setPC(val, thread->readTid());
421 // Squash if we're not already in a state update mode.
422 if (!thread->trapPending && !thread->inSyscall) {
423 cpu->squashFromTC(thread->readTid());
427 template <class Impl>
429 O3ThreadContext<Impl>::setNextPC(uint64_t val)
431 cpu->setNextPC(val, thread->readTid());
433 // Squash if we're not already in a state update mode.
434 if (!thread->trapPending && !thread->inSyscall) {
435 cpu->squashFromTC(thread->readTid());
439 template <class Impl>
441 O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
443 Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid());
445 // Squash if we're not already in a state update mode.
446 if (!thread->trapPending && !thread->inSyscall) {
447 cpu->squashFromTC(thread->readTid());
453 template <class Impl>
455 O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg,
458 Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val,
461 // Squash if we're not already in a state update mode.
462 if (!thread->trapPending && !thread->inSyscall) {
463 cpu->squashFromTC(thread->readTid());
471 template <class Impl>
473 O3ThreadContext<Impl>::getSyscallArg(int i)
475 return cpu->getSyscallArg(i, thread->readTid());
478 template <class Impl>
480 O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val)
482 cpu->setSyscallArg(i, val, thread->readTid());
485 template <class Impl>
487 O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value)
489 cpu->setSyscallReturn(return_value, thread->readTid());
492 #endif // FULL_SYSTEM