2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "cpu/o3/thread_context.hh"
33 #include "cpu/quiesce_event.hh"
35 using namespace TheISA;
40 O3ThreadContext<Impl>::getVirtPort(ThreadContext *src_tc)
43 return thread->getVirtPort();
48 vp = new VirtualPort("tc-vport", src_tc);
49 mem_port = cpu->system->physmem->getPort("functional");
50 mem_port->setPeer(vp);
51 vp->setPeer(mem_port);
57 O3ThreadContext<Impl>::dumpFuncProfile()
59 // Currently not supported
65 O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
67 // some things should already be set up
69 assert(getSystemPtr() == old_context->getSystemPtr());
71 assert(getProcessPtr() == old_context->getProcessPtr());
74 // copy over functional state
75 setStatus(old_context->status());
76 copyArchRegs(old_context);
77 setCpuId(old_context->readCpuId());
80 thread->funcExeInst = old_context->readFuncExeInst();
82 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
84 // Point the quiesce event's TC at this TC so that it wakes up
86 other_quiesce->tc = this;
88 if (thread->quiesceEvent) {
89 thread->quiesceEvent->tc = this;
92 // Transfer kernel stats from one CPU to the other.
93 thread->kernelStats = old_context->getKernelStats();
94 // storeCondFailures = 0;
95 cpu->lockFlag = false;
98 old_context->setStatus(ThreadContext::Unallocated);
100 thread->inSyscall = false;
101 thread->trapPending = false;
105 template <class Impl>
107 O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp)
109 delete vp->getPeer();
114 template <class Impl>
116 O3ThreadContext<Impl>::activate(int delay)
118 DPRINTF(O3CPU, "Calling activate on AlphaTC\n");
120 if (thread->status() == ThreadContext::Active)
124 thread->lastActivate = curTick;
127 if (thread->status() == ThreadContext::Unallocated) {
128 cpu->activateWhenReady(thread->readTid());
132 thread->setStatus(ThreadContext::Active);
134 // status() == Suspended
135 cpu->activateContext(thread->readTid(), delay);
138 template <class Impl>
140 O3ThreadContext<Impl>::suspend()
142 DPRINTF(O3CPU, "Calling suspend on AlphaTC\n");
144 if (thread->status() == ThreadContext::Suspended)
148 thread->lastActivate = curTick;
149 thread->lastSuspend = curTick;
153 // Don't change the status from active if there are pending interrupts
154 if (cpu->check_interrupts()) {
155 assert(status() == ThreadContext::Active);
160 thread->setStatus(ThreadContext::Suspended);
161 cpu->suspendContext(thread->readTid());
164 template <class Impl>
166 O3ThreadContext<Impl>::deallocate()
168 DPRINTF(O3CPU, "Calling deallocate on AlphaTC\n");
170 if (thread->status() == ThreadContext::Unallocated)
173 thread->setStatus(ThreadContext::Unallocated);
174 cpu->deallocateContext(thread->readTid());
177 template <class Impl>
179 O3ThreadContext<Impl>::halt()
181 DPRINTF(O3CPU, "Calling halt on AlphaTC\n");
183 if (thread->status() == ThreadContext::Halted)
186 thread->setStatus(ThreadContext::Halted);
187 cpu->haltContext(thread->readTid());
190 template <class Impl>
192 O3ThreadContext<Impl>::regStats(const std::string &name)
195 thread->kernelStats = new Kernel::Statistics(cpu->system);
196 thread->kernelStats->regStats(name + ".kern");
200 template <class Impl>
202 O3ThreadContext<Impl>::serialize(std::ostream &os)
205 if (thread->kernelStats)
206 thread->kernelStats->serialize(os);
211 template <class Impl>
213 O3ThreadContext<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
216 if (thread->kernelStats)
217 thread->kernelStats->unserialize(cp, section);
223 template <class Impl>
225 O3ThreadContext<Impl>::readLastActivate()
227 return thread->lastActivate;
230 template <class Impl>
232 O3ThreadContext<Impl>::readLastSuspend()
234 return thread->lastSuspend;
237 template <class Impl>
239 O3ThreadContext<Impl>::profileClear()
242 template <class Impl>
244 O3ThreadContext<Impl>::profileSample()
248 template <class Impl>
250 O3ThreadContext<Impl>:: getInst()
252 return thread->getInst();
255 template <class Impl>
257 O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
259 // This function will mess things up unless the ROB is empty and
260 // there are no instructions in the pipeline.
261 unsigned tid = thread->readTid();
262 PhysRegIndex renamed_reg;
264 // First loop through the integer registers.
265 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
266 renamed_reg = cpu->renameMap[tid].lookup(i);
268 DPRINTF(O3CPU, "Copying over register %i, had data %lli, "
269 "now has data %lli.\n",
270 renamed_reg, cpu->readIntReg(renamed_reg),
273 cpu->setIntReg(renamed_reg, tc->readIntReg(i));
276 // Then loop through the floating point registers.
277 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
278 renamed_reg = cpu->renameMap[tid].lookup(i + TheISA::FP_Base_DepTag);
279 cpu->setFloatRegBits(renamed_reg,
280 tc->readFloatRegBits(i));
283 // Copy the misc regs.
284 copyMiscRegs(tc, this);
286 // Then finally set the PC and the next PC.
287 cpu->setPC(tc->readPC(), tid);
288 cpu->setNextPC(tc->readNextPC(), tid);
290 this->thread->funcExeInst = tc->readFuncExeInst();
294 template <class Impl>
296 O3ThreadContext<Impl>::clearArchRegs()
299 template <class Impl>
301 O3ThreadContext<Impl>::readIntReg(int reg_idx)
303 return cpu->readArchIntReg(reg_idx, thread->readTid());
306 template <class Impl>
308 O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
312 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
314 return cpu->readArchFloatRegDouble(reg_idx, thread->readTid());
316 panic("Unsupported width!");
321 template <class Impl>
323 O3ThreadContext<Impl>::readFloatReg(int reg_idx)
325 return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
328 template <class Impl>
330 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
332 DPRINTF(Fault, "Reading floatint register through the TC!\n");
333 return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
336 template <class Impl>
338 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
340 return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
343 template <class Impl>
345 O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
347 cpu->setArchIntReg(reg_idx, val, thread->readTid());
349 // Squash if we're not already in a state update mode.
350 if (!thread->trapPending && !thread->inSyscall) {
351 cpu->squashFromTC(thread->readTid());
355 template <class Impl>
357 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
361 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
364 cpu->setArchFloatRegDouble(reg_idx, val, thread->readTid());
368 // Squash if we're not already in a state update mode.
369 if (!thread->trapPending && !thread->inSyscall) {
370 cpu->squashFromTC(thread->readTid());
374 template <class Impl>
376 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
378 cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
380 if (!thread->trapPending && !thread->inSyscall) {
381 cpu->squashFromTC(thread->readTid());
385 template <class Impl>
387 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
390 DPRINTF(Fault, "Setting floatint register through the TC!\n");
391 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
393 // Squash if we're not already in a state update mode.
394 if (!thread->trapPending && !thread->inSyscall) {
395 cpu->squashFromTC(thread->readTid());
399 template <class Impl>
401 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
403 cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
405 // Squash if we're not already in a state update mode.
406 if (!thread->trapPending && !thread->inSyscall) {
407 cpu->squashFromTC(thread->readTid());
411 template <class Impl>
413 O3ThreadContext<Impl>::setPC(uint64_t val)
415 cpu->setPC(val, thread->readTid());
417 // Squash if we're not already in a state update mode.
418 if (!thread->trapPending && !thread->inSyscall) {
419 cpu->squashFromTC(thread->readTid());
423 template <class Impl>
425 O3ThreadContext<Impl>::setNextPC(uint64_t val)
427 cpu->setNextPC(val, thread->readTid());
429 // Squash if we're not already in a state update mode.
430 if (!thread->trapPending && !thread->inSyscall) {
431 cpu->squashFromTC(thread->readTid());
435 template <class Impl>
437 O3ThreadContext<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
439 Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid());
441 // Squash if we're not already in a state update mode.
442 if (!thread->trapPending && !thread->inSyscall) {
443 cpu->squashFromTC(thread->readTid());
449 template <class Impl>
451 O3ThreadContext<Impl>::setMiscRegWithEffect(int misc_reg,
454 Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val,
457 // Squash if we're not already in a state update mode.
458 if (!thread->trapPending && !thread->inSyscall) {
459 cpu->squashFromTC(thread->readTid());
467 template <class Impl>
469 O3ThreadContext<Impl>::getSyscallArg(int i)
471 return cpu->getSyscallArg(i, thread->readTid());
474 template <class Impl>
476 O3ThreadContext<Impl>::setSyscallArg(int i, IntReg val)
478 cpu->setSyscallArg(i, val, thread->readTid());
481 template <class Impl>
483 O3ThreadContext<Impl>::setSyscallReturn(SyscallReturn return_value)
485 cpu->setSyscallReturn(return_value, thread->readTid());
488 #endif // FULL_SYSTEM