src/cpu/o3/thread_state.hh

   1 /*
   2  * Copyright (c) 2012, 2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __CPU_O3_THREAD_STATE_HH__
  42 #define __CPU_O3_THREAD_STATE_HH__
  43
  44 #include "base/callback.hh"
  45 #include "base/compiler.hh"
  46 #include "base/output.hh"
  47 #include "cpu/thread_context.hh"
  48 #include "cpu/thread_state.hh"
  49 #include "sim/full_system.hh"
  50 #include "sim/sim_exit.hh"
  51
  52 class Event;
  53 class FunctionalMemory;
  54 class Process;
  55
  56 /**
  57  * Class that has various thread state, such as the status, the
  58  * current instruction being processed, whether or not the thread has
  59  * a trap pending or is being externally updated, the ThreadContext
  60  * pointer, etc.  It also handles anything related to a specific
  61  * thread's process, such as syscalls and checking valid addresses.
  62  */
  63 template <class Impl>
  64 struct O3ThreadState : public ThreadState {
  65     typedef ThreadContext::Status Status;
  66     typedef typename Impl::O3CPU O3CPU;
  67
  68   private:
  69     /** Pointer to the CPU. */
  70     O3CPU *cpu;
  71
  72   public:
  73     PCEventQueue pcEventQueue;
  74     /**
  75      * An instruction-based event queue. Used for scheduling events based on
  76      * number of instructions committed.
  77      */
  78     EventQueue comInstEventQueue;
  79
  80     /* This variable controls if writes to a thread context should cause a all
  81      * dynamic/speculative state to be thrown away. Nominally this is the
  82      * desired behavior because the external thread context write has updated
  83      * some state that could be used by an inflight instruction, however there
  84      * are some cases like in a fault/trap handler where this behavior would
  85      * lead to successive restarts and forward progress couldn't be made. This
  86      * variable controls if the squashing will occur.
  87      */
  88     bool noSquashFromTC;
  89
  90     /** Whether or not the thread is currently waiting on a trap, and
  91      * thus able to be externally updated without squashing.
  92      */
  93     bool trapPending;
  94
  95     /** Pointer to the hardware transactional memory checkpoint. */
  96     std::unique_ptr<BaseHTMCheckpoint> htmCheckpoint;
  97
  98     O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process)
  99         : ThreadState(_cpu, _thread_num, _process), cpu(_cpu),
 100           comInstEventQueue("instruction-based event queue"),
 101           noSquashFromTC(false), trapPending(false), tc(nullptr)
 102     {
 103     }
 104
 105     void serialize(CheckpointOut &cp) const override
 106     {
 107         ThreadState::serialize(cp);
 108         // Use the ThreadContext serialization helper to serialize the
 109         // TC.
 110         ::serialize(*tc, cp);
 111     }
 112
 113     void unserialize(CheckpointIn &cp) override
 114     {
 115         // Prevent squashing - we don't have any instructions in
 116         // flight that we need to squash since we just instantiated a
 117         // clean system.
 118         noSquashFromTC = true;
 119         ThreadState::unserialize(cp);
 120         // Use the ThreadContext serialization helper to unserialize
 121         // the TC.
 122         ::unserialize(*tc, cp);
 123         noSquashFromTC = false;
 124     }
 125
 126     /** Pointer to the ThreadContext of this thread. */
 127     ThreadContext *tc;
 128
 129     /** Returns a pointer to the TC of this thread. */
 130     ThreadContext *getTC() { return tc; }
 131
 132     /** Handles the syscall. */
 133     void syscall() { process->syscall(tc); }
 134 };
 135
 136 #endif // __CPU_O3_THREAD_STATE_HH__