src/cpu/op_class.hh

   1 /*
   2  * Copyright (c) 2010, 2017-2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2003-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __CPU__OP_CLASS_HH__
  42 #define __CPU__OP_CLASS_HH__
  43
  44 #include "enums/OpClass.hh"
  45
  46 /*
  47  * Do a bunch of wonky stuff to maintain backward compatability so I
  48  * don't have to change code in a zillion places.
  49  */
  50 using Enums::OpClass;
  51 using Enums::No_OpClass;
  52
  53 static const OpClass IntAluOp = Enums::IntAlu;
  54 static const OpClass IntMultOp = Enums::IntMult;
  55 static const OpClass IntDivOp = Enums::IntDiv;
  56 static const OpClass FloatAddOp = Enums::FloatAdd;
  57 static const OpClass FloatCmpOp = Enums::FloatCmp;
  58 static const OpClass FloatCvtOp = Enums::FloatCvt;
  59 static const OpClass FloatMultOp = Enums::FloatMult;
  60 static const OpClass FloatMultAccOp = Enums::FloatMultAcc;
  61 static const OpClass FloatDivOp = Enums::FloatDiv;
  62 static const OpClass FloatMiscOp = Enums::FloatMisc;
  63 static const OpClass FloatSqrtOp = Enums::FloatSqrt;
  64 static const OpClass SimdAddOp = Enums::SimdAdd;
  65 static const OpClass SimdAddAccOp = Enums::SimdAddAcc;
  66 static const OpClass SimdAluOp = Enums::SimdAlu;
  67 static const OpClass SimdCmpOp = Enums::SimdCmp;
  68 static const OpClass SimdCvtOp = Enums::SimdCvt;
  69 static const OpClass SimdMiscOp = Enums::SimdMisc;
  70 static const OpClass SimdMultOp = Enums::SimdMult;
  71 static const OpClass SimdMultAccOp = Enums::SimdMultAcc;
  72 static const OpClass SimdShiftOp = Enums::SimdShift;
  73 static const OpClass SimdShiftAccOp = Enums::SimdShiftAcc;
  74 static const OpClass SimdDivOp = Enums::SimdDiv;
  75 static const OpClass SimdSqrtOp = Enums::SimdSqrt;
  76 static const OpClass SimdReduceAddOp = Enums::SimdReduceAdd;
  77 static const OpClass SimdReduceAluOp = Enums::SimdReduceAlu;
  78 static const OpClass SimdReduceCmpOp = Enums::SimdReduceCmp;
  79 static const OpClass SimdFloatAddOp = Enums::SimdFloatAdd;
  80 static const OpClass SimdFloatAluOp = Enums::SimdFloatAlu;
  81 static const OpClass SimdFloatCmpOp = Enums::SimdFloatCmp;
  82 static const OpClass SimdFloatCvtOp = Enums::SimdFloatCvt;
  83 static const OpClass SimdFloatDivOp = Enums::SimdFloatDiv;
  84 static const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc;
  85 static const OpClass SimdFloatMultOp = Enums::SimdFloatMult;
  86 static const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc;
  87 static const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt;
  88 static const OpClass SimdFloatReduceCmpOp = Enums::SimdFloatReduceCmp;
  89 static const OpClass SimdFloatReduceAddOp = Enums::SimdFloatReduceAdd;
  90 static const OpClass SimdAesOp = Enums::SimdAes;
  91 static const OpClass SimdAesMixOp = Enums::SimdAesMix;
  92 static const OpClass SimdSha1HashOp = Enums::SimdSha1Hash;
  93 static const OpClass SimdSha1Hash2Op = Enums::SimdSha1Hash2;
  94 static const OpClass SimdSha256HashOp = Enums::SimdSha256Hash;
  95 static const OpClass SimdSha256Hash2Op = Enums::SimdSha256Hash2;
  96 static const OpClass SimdShaSigma2Op = Enums::SimdShaSigma2;
  97 static const OpClass SimdShaSigma3Op = Enums::SimdShaSigma3;
  98 static const OpClass SimdPredAluOp = Enums::SimdPredAlu;
  99 static const OpClass MemReadOp = Enums::MemRead;
 100 static const OpClass MemWriteOp = Enums::MemWrite;
 101 static const OpClass FloatMemReadOp = Enums::FloatMemRead;
 102 static const OpClass FloatMemWriteOp = Enums::FloatMemWrite;
 103 static const OpClass IprAccessOp = Enums::IprAccess;
 104 static const OpClass InstPrefetchOp = Enums::InstPrefetch;
 105 static const OpClass Num_OpClasses = Enums::Num_OpClass;
 106
 107 #endif // __CPU__OP_CLASS_HH__