Port: Stricter port bind/unbind semantics
[gem5.git] / src / cpu / ozone / SimpleOzoneCPU.py
1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
2 # All rights reserved.
3 #
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
14 #
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #
27 # Authors: Kevin Lim
28
29 from m5.defines import buildEnv
30 from m5.params import *
31 from BaseCPU import BaseCPU
32
33 class SimpleOzoneCPU(BaseCPU):
34 type = 'SimpleOzoneCPU'
35
36 numThreads = Param.Unsigned("number of HW thread contexts")
37
38 mem = Param.FunctionalMemory(NULL, "memory")
39
40 width = Param.Unsigned("Width")
41 frontEndWidth = Param.Unsigned("Front end width")
42 backEndWidth = Param.Unsigned("Back end width")
43 backEndSquashLatency = Param.Unsigned("Back end squash latency")
44 backEndLatency = Param.Unsigned("Back end latency")
45 maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
46 decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
47 renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
48 iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
49 "delay")
50 commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
51 fetchWidth = Param.Unsigned("Fetch width")
52
53 renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
54 iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
55 "delay")
56 commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
57 fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
58 decodeWidth = Param.Unsigned("Decode width")
59
60 iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
61 "delay")
62 commitToRenameDelay = Param.Unsigned("Commit to rename delay")
63 decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
64 renameWidth = Param.Unsigned("Rename width")
65
66 commitToIEWDelay = Param.Unsigned("Commit to "
67 "Issue/Execute/Writeback delay")
68 renameToIEWDelay = Param.Unsigned("Rename to "
69 "Issue/Execute/Writeback delay")
70 issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
71 "to the IEW stage)")
72 issueWidth = Param.Unsigned("Issue width")
73 executeWidth = Param.Unsigned("Execute width")
74 executeIntWidth = Param.Unsigned("Integer execute width")
75 executeFloatWidth = Param.Unsigned("Floating point execute width")
76 executeBranchWidth = Param.Unsigned("Branch execute width")
77 executeMemoryWidth = Param.Unsigned("Memory execute width")
78
79 iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
80 "delay")
81 renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
82 commitWidth = Param.Unsigned("Commit width")
83 squashWidth = Param.Unsigned("Squash width")
84
85 localPredictorSize = Param.Unsigned("Size of local predictor")
86 localCtrBits = Param.Unsigned("Bits per counter")
87 localHistoryTableSize = Param.Unsigned("Size of local history table")
88 localHistoryBits = Param.Unsigned("Bits for the local history")
89 globalPredictorSize = Param.Unsigned("Size of global predictor")
90 globalCtrBits = Param.Unsigned("Bits per counter")
91 globalHistoryBits = Param.Unsigned("Bits of history")
92 choicePredictorSize = Param.Unsigned("Size of choice predictor")
93 choiceCtrBits = Param.Unsigned("Bits of choice counters")
94
95 BTBEntries = Param.Unsigned("Number of BTB entries")
96 BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
97
98 RASSize = Param.Unsigned("RAS size")
99
100 LQEntries = Param.Unsigned("Number of load queue entries")
101 SQEntries = Param.Unsigned("Number of store queue entries")
102 LFSTSize = Param.Unsigned("Last fetched store table size")
103 SSITSize = Param.Unsigned("Store set ID table size")
104
105 numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
106 numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
107 "registers")
108 numIQEntries = Param.Unsigned("Number of instruction queue entries")
109 numROBEntries = Param.Unsigned("Number of reorder buffer entries")
110
111 instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")