2 * Copyright (c) 2006 The Regents of The University of Michigan
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31 #ifndef __CPU_OZONE_CPU_HH__
32 #define __CPU_OZONE_CPU_HH__
36 #include "arch/alpha/tlb.hh"
37 #include "base/statistics.hh"
38 #include "config/the_isa.hh"
39 #include "cpu/ozone/rename_table.hh"
40 #include "cpu/ozone/thread_state.hh"
41 #include "cpu/base.hh"
42 #include "cpu/inst_seq.hh"
43 #include "cpu/pc_event.hh"
44 #include "cpu/static_inst.hh"
45 #include "cpu/thread_context.hh"
46 #include "cpu/timebuf.hh"
47 #include "mem/page_table.hh"
48 #include "sim/eventq.hh"
50 // forward declarations
60 class EndQuiesceEvent;
61 class MemoryController;
74 * Light weight out of order CPU model that approximates an out of
75 * order CPU. It is separated into a front end and a back end, with
76 * the template parameter Impl describing the classes used for each.
77 * The goal is to be able to specify through the Impl the class to use
78 * for the front end and back end, with different classes used to
79 * model different levels of detail.
82 class OzoneCPU : public BaseCPU
85 typedef typename Impl::FrontEnd FrontEnd;
86 typedef typename Impl::BackEnd BackEnd;
87 typedef typename Impl::DynInst DynInst;
88 typedef typename Impl::DynInstPtr DynInstPtr;
90 typedef TheISA::FloatReg FloatReg;
91 typedef TheISA::FloatRegBits FloatRegBits;
92 typedef TheISA::MiscReg MiscReg;
95 class OzoneTC : public ThreadContext {
99 OzoneThreadState<Impl> *thread;
101 BaseCPU *getCpuPtr();
103 TheISA::TLB *getITBPtr() { return cpu->itb; }
105 TheISA::TLB * getDTBPtr() { return cpu->dtb; }
107 System *getSystemPtr() { return cpu->system; }
109 TheISA::Kernel::Statistics *getKernelStats()
110 { return thread->getKernelStats(); }
112 Process *getProcessPtr() { return thread->getProcessPtr(); }
114 PortProxy &getPhysProxy() { return thread->getPhysProxy(); }
116 FSTranslatingPortProxy &getVirtProxy()
117 { return thread->getVirtProxy(); }
119 SETranslatingPortProxy &getMemProxy() { return thread->getMemProxy(); }
121 Status status() const { return thread->status(); }
123 void setStatus(Status new_status);
125 /// Set the status to Active. Optional delay indicates number of
126 /// cycles to wait before beginning execution.
127 void activate(int delay = 1);
129 /// Set the status to Suspended.
132 /// Set the status to Halted.
135 void dumpFuncProfile();
137 void takeOverFrom(ThreadContext *old_context);
139 void regStats(const std::string &name);
141 void serialize(std::ostream &os);
142 void unserialize(Checkpoint *cp, const std::string §ion);
144 EndQuiesceEvent *getQuiesceEvent();
146 Tick readLastActivate();
147 Tick readLastSuspend();
150 void profileSample();
154 void copyArchRegs(ThreadContext *tc);
156 void clearArchRegs();
158 uint64_t readIntReg(int reg_idx);
160 FloatReg readFloatReg(int reg_idx);
162 FloatRegBits readFloatRegBits(int reg_idx);
164 void setIntReg(int reg_idx, uint64_t val);
166 void setFloatReg(int reg_idx, FloatReg val);
168 void setFloatRegBits(int reg_idx, FloatRegBits val);
170 uint64_t readPC() { return thread->PC; }
171 void setPC(Addr val);
173 uint64_t readNextPC() { return thread->nextPC; }
174 void setNextPC(Addr val);
176 uint64_t readNextNPC()
178 #if ISA_HAS_DELAY_SLOT
179 panic("Ozone needs to support nextNPC");
181 return thread->nextPC + sizeof(TheISA::MachInst);
185 void setNextNPC(uint64_t val)
187 #if ISA_HAS_DELAY_SLOT
188 panic("Ozone needs to support nextNPC");
194 MiscReg readMiscRegNoEffect(int misc_reg);
196 MiscReg readMiscReg(int misc_reg);
198 void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
200 void setMiscReg(int misc_reg, const MiscReg &val);
202 unsigned readStCondFailures()
203 { return thread->storeCondFailures; }
205 void setStCondFailures(unsigned sc_failures)
206 { thread->storeCondFailures = sc_failures; }
208 bool misspeculating() { return false; }
210 Counter readFuncExeInst() { return thread->funcExeInst; }
212 void setFuncExeInst(Counter new_val)
213 { thread->funcExeInst = new_val; }
216 // Ozone specific thread context
218 // Thread context to be used
220 // Checker thread context; will wrap the OzoneTC if a checker is
222 ThreadContext *checkerTC;
224 typedef OzoneThreadState<Impl> ImplState;
227 // Committed thread state for the OzoneCPU.
228 OzoneThreadState<Impl> thread;
231 // main simulation loop (one cycle)
235 /** Count of total number of dynamic instructions in flight. */
239 std::set<InstSeqNum> snList;
240 std::set<Addr> lockAddrList;
242 struct TickEvent : public Event
247 TickEvent(OzoneCPU *c, int w);
249 const char *description() const;
254 /// Schedule tick event, regardless of its current state.
255 void scheduleTickEvent(int delay)
257 if (tickEvent.squashed())
258 tickEvent.reschedule(curTick() + ticks(delay));
259 else if (!tickEvent.scheduled())
260 tickEvent.schedule(curTick() + ticks(delay));
263 /// Unschedule tick event, regardless of its current state.
264 void unscheduleTickEvent()
266 if (tickEvent.scheduled())
282 void zero_fill_64(Addr addr) {
283 static int warned = 0;
285 warn ("WH64 is not implemented");
290 typedef typename Impl::Params Params;
292 OzoneCPU(Params *params);
299 BaseCPU *getCpuPtr() { return this; }
302 void signalSwitched();
303 void takeOverFrom(BaseCPU *oldCPU);
307 Addr dbg_vtophys(Addr addr);
320 Status status() const { return _status; }
321 void setStatus(Status new_status) { _status = new_status; }
323 virtual void activateContext(int thread_num, int delay);
324 virtual void suspendContext(int thread_num);
325 virtual void deallocateContext(int thread_num, int delay);
326 virtual void haltContext(int thread_num);
329 virtual void regStats();
330 virtual void resetStats();
332 // number of simulated instructions
335 Counter startNumInst;
337 virtual Counter totalInstructions() const
339 return numInst - startNumInst;
343 // number of simulated loads
345 Counter startNumLoad;
347 // number of idle cycles
348 Stats::Average notIdleFraction;
349 Stats::Formula idleFraction;
352 virtual void serialize(std::ostream &os);
353 virtual void unserialize(Checkpoint *cp, const std::string §ion);
355 void demapPage(Addr vaddr, uint64_t asn)
357 cpu->itb->demap(vaddr, asn);
358 cpu->dtb->demap(vaddr, asn);
361 void demapInstPage(Addr vaddr, uint64_t asn)
363 cpu->itb->demap(vaddr, asn);
366 void demapDataPage(Addr vaddr, uint64_t asn)
368 cpu->dtb->demap(vaddr, asn);
371 /** CPU read function, forwards read to LSQ. */
373 Fault read(Request *req, T &data, int load_idx)
375 return backEnd->read(req, data, load_idx);
378 /** CPU write function, forwards write to LSQ. */
380 Fault write(Request *req, T &data, int store_idx)
382 return backEnd->write(req, data, store_idx);
388 void dumpInsts() { frontEnd->dumpInsts(); }
391 bool simPalCheck(int palFunc);
392 void processInterrupts();
393 void syscall(uint64_t &callnum);
395 ThreadContext *tcBase() { return tc; }
398 InstSeqNum doneSeqNum;
399 InstSeqNum nonSpecSeqNum;
406 InstSeqNum globalSeqNum;
408 TimeBuffer<CommStruct> comm;
410 bool decoupledFrontEnd;
414 Stats::Scalar quiesceCycles;
416 Checker<DynInstPtr> *checker;
419 #endif // __CPU_OZONE_CPU_HH__