src/cpu/ozone/cpu_builder.cc

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include <string>
  32
  33 #include "cpu/checker/cpu.hh"
  34 #include "cpu/inst_seq.hh"
  35 #include "cpu/ozone/cpu.hh"
  36 #include "cpu/ozone/ozone_impl.hh"
  37 #include "cpu/ozone/simple_impl.hh"
  38 #include "cpu/ozone/simple_params.hh"
  39 #include "mem/cache/base_cache.hh"
  40 #include "sim/builder.hh"
  41 #include "sim/process.hh"
  42 #include "sim/sim_object.hh"
  43
  44 class DerivOzoneCPU : public OzoneCPU<OzoneImpl>
  45 {
  46   public:
  47     DerivOzoneCPU(SimpleParams *p)
  48         : OzoneCPU<OzoneImpl>(p)
  49     { }
  50 };
  51
  52 class SimpleOzoneCPU : public OzoneCPU<SimpleImpl>
  53 {
  54   public:
  55     SimpleOzoneCPU(SimpleParams *p)
  56         : OzoneCPU<SimpleImpl>(p)
  57     { }
  58 };
  59
  60
  61 ////////////////////////////////////////////////////////////////////////
  62 //
  63 //  OzoneCPU Simulation Object
  64 //
  65
  66 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
  67
  68     Param<int> clock;
  69     Param<int> numThreads;
  70
  71 #if FULL_SYSTEM
  72 SimObjectParam<System *> system;
  73 Param<int> cpu_id;
  74 SimObjectParam<AlphaITB *> itb;
  75 SimObjectParam<AlphaDTB *> dtb;
  76 #else
  77 SimObjectVectorParam<Process *> workload;
  78 //SimObjectParam<PageTable *> page_table;
  79 #endif // FULL_SYSTEM
  80
  81 SimObjectParam<FunctionalMemory *> mem;
  82
  83 SimObjectParam<BaseCPU *> checker;
  84
  85 Param<Counter> max_insts_any_thread;
  86 Param<Counter> max_insts_all_threads;
  87 Param<Counter> max_loads_any_thread;
  88 Param<Counter> max_loads_all_threads;
  89
  90 SimObjectParam<BaseCache *> icache;
  91 SimObjectParam<BaseCache *> dcache;
  92
  93 Param<unsigned> cachePorts;
  94 Param<unsigned> width;
  95 Param<unsigned> frontEndWidth;
  96 Param<unsigned> backEndWidth;
  97 Param<unsigned> backEndSquashLatency;
  98 Param<unsigned> backEndLatency;
  99 Param<unsigned> maxInstBufferSize;
 100 Param<unsigned> numPhysicalRegs;
 101 Param<unsigned> maxOutstandingMemOps;
 102
 103 Param<unsigned> decodeToFetchDelay;
 104 Param<unsigned> renameToFetchDelay;
 105 Param<unsigned> iewToFetchDelay;
 106 Param<unsigned> commitToFetchDelay;
 107 Param<unsigned> fetchWidth;
 108
 109 Param<unsigned> renameToDecodeDelay;
 110 Param<unsigned> iewToDecodeDelay;
 111 Param<unsigned> commitToDecodeDelay;
 112 Param<unsigned> fetchToDecodeDelay;
 113 Param<unsigned> decodeWidth;
 114
 115 Param<unsigned> iewToRenameDelay;
 116 Param<unsigned> commitToRenameDelay;
 117 Param<unsigned> decodeToRenameDelay;
 118 Param<unsigned> renameWidth;
 119
 120 Param<unsigned> commitToIEWDelay;
 121 Param<unsigned> renameToIEWDelay;
 122 Param<unsigned> issueToExecuteDelay;
 123 Param<unsigned> issueWidth;
 124 Param<unsigned> executeWidth;
 125 Param<unsigned> executeIntWidth;
 126 Param<unsigned> executeFloatWidth;
 127 Param<unsigned> executeBranchWidth;
 128 Param<unsigned> executeMemoryWidth;
 129
 130 Param<unsigned> iewToCommitDelay;
 131 Param<unsigned> renameToROBDelay;
 132 Param<unsigned> commitWidth;
 133 Param<unsigned> squashWidth;
 134
 135 Param<std::string> predType;
 136 Param<unsigned> localPredictorSize;
 137 Param<unsigned> localCtrBits;
 138 Param<unsigned> localHistoryTableSize;
 139 Param<unsigned> localHistoryBits;
 140 Param<unsigned> globalPredictorSize;
 141 Param<unsigned> globalCtrBits;
 142 Param<unsigned> globalHistoryBits;
 143 Param<unsigned> choicePredictorSize;
 144 Param<unsigned> choiceCtrBits;
 145
 146 Param<unsigned> BTBEntries;
 147 Param<unsigned> BTBTagSize;
 148
 149 Param<unsigned> RASSize;
 150
 151 Param<unsigned> LQEntries;
 152 Param<unsigned> SQEntries;
 153 Param<unsigned> LFSTSize;
 154 Param<unsigned> SSITSize;
 155
 156 Param<unsigned> numPhysIntRegs;
 157 Param<unsigned> numPhysFloatRegs;
 158 Param<unsigned> numIQEntries;
 159 Param<unsigned> numROBEntries;
 160
 161 Param<bool> decoupledFrontEnd;
 162 Param<int> dispatchWidth;
 163 Param<int> wbWidth;
 164
 165 Param<unsigned> smtNumFetchingThreads;
 166 Param<std::string>   smtFetchPolicy;
 167 Param<std::string>   smtLSQPolicy;
 168 Param<unsigned> smtLSQThreshold;
 169 Param<std::string>   smtIQPolicy;
 170 Param<unsigned> smtIQThreshold;
 171 Param<std::string>   smtROBPolicy;
 172 Param<unsigned> smtROBThreshold;
 173 Param<std::string>   smtCommitPolicy;
 174
 175 Param<unsigned> instShiftAmt;
 176
 177 Param<bool> defer_registration;
 178
 179 Param<bool> function_trace;
 180 Param<Tick> function_trace_start;
 181
 182 END_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
 183
 184 BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
 185
 186     INIT_PARAM(clock, "clock speed"),
 187     INIT_PARAM(numThreads, "number of HW thread contexts"),
 188
 189 #if FULL_SYSTEM
 190     INIT_PARAM(system, "System object"),
 191     INIT_PARAM(cpu_id, "processor ID"),
 192     INIT_PARAM(itb, "Instruction translation buffer"),
 193     INIT_PARAM(dtb, "Data translation buffer"),
 194 #else
 195     INIT_PARAM(workload, "Processes to run"),
 196 //    INIT_PARAM(page_table, "Page table"),
 197 #endif // FULL_SYSTEM
 198
 199     INIT_PARAM_DFLT(mem, "Memory", NULL),
 200
 201     INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
 202
 203     INIT_PARAM_DFLT(max_insts_any_thread,
 204                     "Terminate when any thread reaches this inst count",
 205                     0),
 206     INIT_PARAM_DFLT(max_insts_all_threads,
 207                     "Terminate when all threads have reached"
 208                     "this inst count",
 209                     0),
 210     INIT_PARAM_DFLT(max_loads_any_thread,
 211                     "Terminate when any thread reaches this load count",
 212                     0),
 213     INIT_PARAM_DFLT(max_loads_all_threads,
 214                     "Terminate when all threads have reached this load"
 215                     "count",
 216                     0),
 217
 218     INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
 219     INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
 220
 221     INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
 222     INIT_PARAM_DFLT(width, "Width", 1),
 223     INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
 224     INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
 225     INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
 226     INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
 227     INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
 228     INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
 229     INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
 230
 231     INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
 232     INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
 233     INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
 234                "delay"),
 235     INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
 236     INIT_PARAM(fetchWidth, "Fetch width"),
 237     INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
 238     INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
 239                "delay"),
 240     INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
 241     INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
 242     INIT_PARAM(decodeWidth, "Decode width"),
 243
 244     INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
 245                "delay"),
 246     INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
 247     INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
 248     INIT_PARAM(renameWidth, "Rename width"),
 249
 250     INIT_PARAM(commitToIEWDelay, "Commit to "
 251                "Issue/Execute/Writeback delay"),
 252     INIT_PARAM(renameToIEWDelay, "Rename to "
 253                "Issue/Execute/Writeback delay"),
 254     INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
 255                "to the IEW stage)"),
 256     INIT_PARAM(issueWidth, "Issue width"),
 257     INIT_PARAM(executeWidth, "Execute width"),
 258     INIT_PARAM(executeIntWidth, "Integer execute width"),
 259     INIT_PARAM(executeFloatWidth, "Floating point execute width"),
 260     INIT_PARAM(executeBranchWidth, "Branch execute width"),
 261     INIT_PARAM(executeMemoryWidth, "Memory execute width"),
 262
 263     INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
 264                "delay"),
 265     INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
 266     INIT_PARAM(commitWidth, "Commit width"),
 267     INIT_PARAM(squashWidth, "Squash width"),
 268
 269     INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
 270     INIT_PARAM(localPredictorSize, "Size of local predictor"),
 271     INIT_PARAM(localCtrBits, "Bits per counter"),
 272     INIT_PARAM(localHistoryTableSize, "Size of local history table"),
 273     INIT_PARAM(localHistoryBits, "Bits for the local history"),
 274     INIT_PARAM(globalPredictorSize, "Size of global predictor"),
 275     INIT_PARAM(globalCtrBits, "Bits per counter"),
 276     INIT_PARAM(globalHistoryBits, "Bits of history"),
 277     INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
 278     INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
 279
 280     INIT_PARAM(BTBEntries, "Number of BTB entries"),
 281     INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
 282
 283     INIT_PARAM(RASSize, "RAS size"),
 284
 285     INIT_PARAM(LQEntries, "Number of load queue entries"),
 286     INIT_PARAM(SQEntries, "Number of store queue entries"),
 287     INIT_PARAM(LFSTSize, "Last fetched store table size"),
 288     INIT_PARAM(SSITSize, "Store set ID table size"),
 289
 290     INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
 291     INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
 292                "registers"),
 293     INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
 294     INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
 295
 296     INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
 297     INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
 298     INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
 299
 300     INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
 301     INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
 302     INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
 303     INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
 304     INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
 305     INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
 306     INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
 307     INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
 308     INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
 309
 310     INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
 311     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 312
 313     INIT_PARAM(function_trace, "Enable function trace"),
 314     INIT_PARAM(function_trace_start, "Cycle to start function trace")
 315
 316 END_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
 317
 318 CREATE_SIM_OBJECT(DerivOzoneCPU)
 319 {
 320     DerivOzoneCPU *cpu;
 321
 322 #if FULL_SYSTEM
 323     // Full-system only supports a single thread for the moment.
 324     int actual_num_threads = 1;
 325 #else
 326     // In non-full-system mode, we infer the number of threads from
 327     // the workload if it's not explicitly specified.
 328     int actual_num_threads =
 329         numThreads.isValid() ? numThreads : workload.size();
 330
 331     if (workload.size() == 0) {
 332         fatal("Must specify at least one workload!");
 333     }
 334
 335 #endif
 336
 337     SimpleParams *params = new SimpleParams;
 338
 339     params->clock = clock;
 340
 341     params->name = getInstanceName();
 342     params->numberOfThreads = actual_num_threads;
 343
 344 #if FULL_SYSTEM
 345     params->system = system;
 346     params->cpu_id = cpu_id;
 347     params->itb = itb;
 348     params->dtb = dtb;
 349 #else
 350     params->workload = workload;
 351 //    params->pTable = page_table;
 352 #endif // FULL_SYSTEM
 353
 354     params->mem = mem;
 355     params->checker = checker;
 356     params->max_insts_any_thread = max_insts_any_thread;
 357     params->max_insts_all_threads = max_insts_all_threads;
 358     params->max_loads_any_thread = max_loads_any_thread;
 359     params->max_loads_all_threads = max_loads_all_threads;
 360
 361     //
 362     // Caches
 363     //
 364     params->icacheInterface = icache ? icache->getInterface() : NULL;
 365     params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
 366     params->cachePorts = cachePorts;
 367
 368     params->width = width;
 369     params->frontEndWidth = frontEndWidth;
 370     params->backEndWidth = backEndWidth;
 371     params->backEndSquashLatency = backEndSquashLatency;
 372     params->backEndLatency = backEndLatency;
 373     params->maxInstBufferSize = maxInstBufferSize;
 374     params->numPhysicalRegs = numPhysIntRegs + numPhysFloatRegs;
 375     params->maxOutstandingMemOps = maxOutstandingMemOps;
 376
 377     params->decodeToFetchDelay = decodeToFetchDelay;
 378     params->renameToFetchDelay = renameToFetchDelay;
 379     params->iewToFetchDelay = iewToFetchDelay;
 380     params->commitToFetchDelay = commitToFetchDelay;
 381     params->fetchWidth = fetchWidth;
 382
 383     params->renameToDecodeDelay = renameToDecodeDelay;
 384     params->iewToDecodeDelay = iewToDecodeDelay;
 385     params->commitToDecodeDelay = commitToDecodeDelay;
 386     params->fetchToDecodeDelay = fetchToDecodeDelay;
 387     params->decodeWidth = decodeWidth;
 388
 389     params->iewToRenameDelay = iewToRenameDelay;
 390     params->commitToRenameDelay = commitToRenameDelay;
 391     params->decodeToRenameDelay = decodeToRenameDelay;
 392     params->renameWidth = renameWidth;
 393
 394     params->commitToIEWDelay = commitToIEWDelay;
 395     params->renameToIEWDelay = renameToIEWDelay;
 396     params->issueToExecuteDelay = issueToExecuteDelay;
 397     params->issueWidth = issueWidth;
 398     params->executeWidth = executeWidth;
 399     params->executeIntWidth = executeIntWidth;
 400     params->executeFloatWidth = executeFloatWidth;
 401     params->executeBranchWidth = executeBranchWidth;
 402     params->executeMemoryWidth = executeMemoryWidth;
 403
 404     params->iewToCommitDelay = iewToCommitDelay;
 405     params->renameToROBDelay = renameToROBDelay;
 406     params->commitWidth = commitWidth;
 407     params->squashWidth = squashWidth;
 408
 409     params->predType = predType;
 410     params->localPredictorSize = localPredictorSize;
 411     params->localCtrBits = localCtrBits;
 412     params->localHistoryTableSize = localHistoryTableSize;
 413     params->localHistoryBits = localHistoryBits;
 414     params->globalPredictorSize = globalPredictorSize;
 415     params->globalCtrBits = globalCtrBits;
 416     params->globalHistoryBits = globalHistoryBits;
 417     params->choicePredictorSize = choicePredictorSize;
 418     params->choiceCtrBits = choiceCtrBits;
 419
 420     params->BTBEntries = BTBEntries;
 421     params->BTBTagSize = BTBTagSize;
 422
 423     params->RASSize = RASSize;
 424
 425     params->LQEntries = LQEntries;
 426     params->SQEntries = SQEntries;
 427
 428     params->SSITSize = SSITSize;
 429     params->LFSTSize = LFSTSize;
 430
 431     params->numPhysIntRegs = numPhysIntRegs;
 432     params->numPhysFloatRegs = numPhysFloatRegs;
 433     params->numIQEntries = numIQEntries;
 434     params->numROBEntries = numROBEntries;
 435
 436     params->decoupledFrontEnd = decoupledFrontEnd;
 437     params->dispatchWidth = dispatchWidth;
 438     params->wbWidth = wbWidth;
 439
 440     params->smtNumFetchingThreads = smtNumFetchingThreads;
 441     params->smtFetchPolicy = smtFetchPolicy;
 442     params->smtIQPolicy    = smtIQPolicy;
 443     params->smtLSQPolicy    = smtLSQPolicy;
 444     params->smtLSQThreshold = smtLSQThreshold;
 445     params->smtROBPolicy   = smtROBPolicy;
 446     params->smtROBThreshold = smtROBThreshold;
 447     params->smtCommitPolicy = smtCommitPolicy;
 448
 449     params->instShiftAmt = 2;
 450
 451     params->deferRegistration = defer_registration;
 452
 453     params->functionTrace = function_trace;
 454     params->functionTraceStart = function_trace_start;
 455
 456     cpu = new DerivOzoneCPU(params);
 457
 458     return cpu;
 459 }
 460
 461 REGISTER_SIM_OBJECT("DerivOzoneCPU", DerivOzoneCPU)
 462
 463
 464
 465 ////////////////////////////////////////////////////////////////////////
 466 //
 467 //  OzoneCPU Simulation Object
 468 //
 469
 470 BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
 471
 472     Param<int> clock;
 473     Param<int> numThreads;
 474
 475 #if FULL_SYSTEM
 476 SimObjectParam<System *> system;
 477 Param<int> cpu_id;
 478 SimObjectParam<AlphaITB *> itb;
 479 SimObjectParam<AlphaDTB *> dtb;
 480 #else
 481 SimObjectVectorParam<Process *> workload;
 482 //SimObjectParam<PageTable *> page_table;
 483 #endif // FULL_SYSTEM
 484
 485 SimObjectParam<FunctionalMemory *> mem;
 486
 487 SimObjectParam<BaseCPU *> checker;
 488
 489 Param<Counter> max_insts_any_thread;
 490 Param<Counter> max_insts_all_threads;
 491 Param<Counter> max_loads_any_thread;
 492 Param<Counter> max_loads_all_threads;
 493
 494 SimObjectParam<BaseCache *> icache;
 495 SimObjectParam<BaseCache *> dcache;
 496
 497 Param<unsigned> cachePorts;
 498 Param<unsigned> width;
 499 Param<unsigned> frontEndWidth;
 500 Param<unsigned> backEndWidth;
 501 Param<unsigned> backEndSquashLatency;
 502 Param<unsigned> backEndLatency;
 503 Param<unsigned> maxInstBufferSize;
 504 Param<unsigned> numPhysicalRegs;
 505
 506 Param<unsigned> decodeToFetchDelay;
 507 Param<unsigned> renameToFetchDelay;
 508 Param<unsigned> iewToFetchDelay;
 509 Param<unsigned> commitToFetchDelay;
 510 Param<unsigned> fetchWidth;
 511
 512 Param<unsigned> renameToDecodeDelay;
 513 Param<unsigned> iewToDecodeDelay;
 514 Param<unsigned> commitToDecodeDelay;
 515 Param<unsigned> fetchToDecodeDelay;
 516 Param<unsigned> decodeWidth;
 517
 518 Param<unsigned> iewToRenameDelay;
 519 Param<unsigned> commitToRenameDelay;
 520 Param<unsigned> decodeToRenameDelay;
 521 Param<unsigned> renameWidth;
 522
 523 Param<unsigned> commitToIEWDelay;
 524 Param<unsigned> renameToIEWDelay;
 525 Param<unsigned> issueToExecuteDelay;
 526 Param<unsigned> issueWidth;
 527 Param<unsigned> executeWidth;
 528 Param<unsigned> executeIntWidth;
 529 Param<unsigned> executeFloatWidth;
 530 Param<unsigned> executeBranchWidth;
 531 Param<unsigned> executeMemoryWidth;
 532
 533 Param<unsigned> iewToCommitDelay;
 534 Param<unsigned> renameToROBDelay;
 535 Param<unsigned> commitWidth;
 536 Param<unsigned> squashWidth;
 537
 538 Param<std::string> predType;
 539 Param<unsigned> localPredictorSize;
 540 Param<unsigned> localCtrBits;
 541 Param<unsigned> localHistoryTableSize;
 542 Param<unsigned> localHistoryBits;
 543 Param<unsigned> globalPredictorSize;
 544 Param<unsigned> globalCtrBits;
 545 Param<unsigned> globalHistoryBits;
 546 Param<unsigned> choicePredictorSize;
 547 Param<unsigned> choiceCtrBits;
 548
 549 Param<unsigned> BTBEntries;
 550 Param<unsigned> BTBTagSize;
 551
 552 Param<unsigned> RASSize;
 553
 554 Param<unsigned> LQEntries;
 555 Param<unsigned> SQEntries;
 556 Param<unsigned> LFSTSize;
 557 Param<unsigned> SSITSize;
 558
 559 Param<unsigned> numPhysIntRegs;
 560 Param<unsigned> numPhysFloatRegs;
 561 Param<unsigned> numIQEntries;
 562 Param<unsigned> numROBEntries;
 563
 564 Param<bool> decoupledFrontEnd;
 565 Param<int> dispatchWidth;
 566 Param<int> wbWidth;
 567
 568 Param<unsigned> smtNumFetchingThreads;
 569 Param<std::string>   smtFetchPolicy;
 570 Param<std::string>   smtLSQPolicy;
 571 Param<unsigned> smtLSQThreshold;
 572 Param<std::string>   smtIQPolicy;
 573 Param<unsigned> smtIQThreshold;
 574 Param<std::string>   smtROBPolicy;
 575 Param<unsigned> smtROBThreshold;
 576 Param<std::string>   smtCommitPolicy;
 577
 578 Param<unsigned> instShiftAmt;
 579
 580 Param<bool> defer_registration;
 581
 582 Param<bool> function_trace;
 583 Param<Tick> function_trace_start;
 584
 585 END_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
 586
 587 BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
 588
 589     INIT_PARAM(clock, "clock speed"),
 590     INIT_PARAM(numThreads, "number of HW thread contexts"),
 591
 592 #if FULL_SYSTEM
 593     INIT_PARAM(system, "System object"),
 594     INIT_PARAM(cpu_id, "processor ID"),
 595     INIT_PARAM(itb, "Instruction translation buffer"),
 596     INIT_PARAM(dtb, "Data translation buffer"),
 597 #else
 598     INIT_PARAM(workload, "Processes to run"),
 599 //    INIT_PARAM(page_table, "Page table"),
 600 #endif // FULL_SYSTEM
 601
 602     INIT_PARAM_DFLT(mem, "Memory", NULL),
 603
 604     INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
 605
 606     INIT_PARAM_DFLT(max_insts_any_thread,
 607                     "Terminate when any thread reaches this inst count",
 608                     0),
 609     INIT_PARAM_DFLT(max_insts_all_threads,
 610                     "Terminate when all threads have reached"
 611                     "this inst count",
 612                     0),
 613     INIT_PARAM_DFLT(max_loads_any_thread,
 614                     "Terminate when any thread reaches this load count",
 615                     0),
 616     INIT_PARAM_DFLT(max_loads_all_threads,
 617                     "Terminate when all threads have reached this load"
 618                     "count",
 619                     0),
 620
 621     INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
 622     INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
 623
 624     INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
 625     INIT_PARAM_DFLT(width, "Width", 1),
 626     INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
 627     INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
 628     INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
 629     INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
 630     INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
 631     INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
 632
 633     INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
 634     INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
 635     INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
 636                "delay"),
 637     INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
 638     INIT_PARAM(fetchWidth, "Fetch width"),
 639     INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
 640     INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
 641                "delay"),
 642     INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
 643     INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
 644     INIT_PARAM(decodeWidth, "Decode width"),
 645
 646     INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
 647                "delay"),
 648     INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
 649     INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
 650     INIT_PARAM(renameWidth, "Rename width"),
 651
 652     INIT_PARAM(commitToIEWDelay, "Commit to "
 653                "Issue/Execute/Writeback delay"),
 654     INIT_PARAM(renameToIEWDelay, "Rename to "
 655                "Issue/Execute/Writeback delay"),
 656     INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
 657                "to the IEW stage)"),
 658     INIT_PARAM(issueWidth, "Issue width"),
 659     INIT_PARAM(executeWidth, "Execute width"),
 660     INIT_PARAM(executeIntWidth, "Integer execute width"),
 661     INIT_PARAM(executeFloatWidth, "Floating point execute width"),
 662     INIT_PARAM(executeBranchWidth, "Branch execute width"),
 663     INIT_PARAM(executeMemoryWidth, "Memory execute width"),
 664
 665     INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
 666                "delay"),
 667     INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
 668     INIT_PARAM(commitWidth, "Commit width"),
 669     INIT_PARAM(squashWidth, "Squash width"),
 670
 671     INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
 672     INIT_PARAM(localPredictorSize, "Size of local predictor"),
 673     INIT_PARAM(localCtrBits, "Bits per counter"),
 674     INIT_PARAM(localHistoryTableSize, "Size of local history table"),
 675     INIT_PARAM(localHistoryBits, "Bits for the local history"),
 676     INIT_PARAM(globalPredictorSize, "Size of global predictor"),
 677     INIT_PARAM(globalCtrBits, "Bits per counter"),
 678     INIT_PARAM(globalHistoryBits, "Bits of history"),
 679     INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
 680     INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
 681
 682     INIT_PARAM(BTBEntries, "Number of BTB entries"),
 683     INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
 684
 685     INIT_PARAM(RASSize, "RAS size"),
 686
 687     INIT_PARAM(LQEntries, "Number of load queue entries"),
 688     INIT_PARAM(SQEntries, "Number of store queue entries"),
 689     INIT_PARAM(LFSTSize, "Last fetched store table size"),
 690     INIT_PARAM(SSITSize, "Store set ID table size"),
 691
 692     INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
 693     INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
 694                "registers"),
 695     INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
 696     INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
 697
 698     INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
 699     INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
 700     INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
 701
 702     INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
 703     INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
 704     INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
 705     INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
 706     INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
 707     INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
 708     INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
 709     INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
 710     INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
 711
 712     INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
 713     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 714
 715     INIT_PARAM(function_trace, "Enable function trace"),
 716     INIT_PARAM(function_trace_start, "Cycle to start function trace")
 717
 718 END_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
 719
 720 CREATE_SIM_OBJECT(SimpleOzoneCPU)
 721 {
 722     SimpleOzoneCPU *cpu;
 723
 724 #if FULL_SYSTEM
 725     // Full-system only supports a single thread for the moment.
 726     int actual_num_threads = 1;
 727 #else
 728     // In non-full-system mode, we infer the number of threads from
 729     // the workload if it's not explicitly specified.
 730     int actual_num_threads =
 731         numThreads.isValid() ? numThreads : workload.size();
 732
 733     if (workload.size() == 0) {
 734         fatal("Must specify at least one workload!");
 735     }
 736
 737 #endif
 738
 739     SimpleParams *params = new SimpleParams;
 740
 741     params->clock = clock;
 742
 743     params->name = getInstanceName();
 744     params->numberOfThreads = actual_num_threads;
 745
 746 #if FULL_SYSTEM
 747     params->system = system;
 748     params->cpu_id = cpu_id;
 749     params->itb = itb;
 750     params->dtb = dtb;
 751 #else
 752     params->workload = workload;
 753 //    params->pTable = page_table;
 754 #endif // FULL_SYSTEM
 755
 756     params->mem = mem;
 757     params->checker = checker;
 758     params->max_insts_any_thread = max_insts_any_thread;
 759     params->max_insts_all_threads = max_insts_all_threads;
 760     params->max_loads_any_thread = max_loads_any_thread;
 761     params->max_loads_all_threads = max_loads_all_threads;
 762
 763     //
 764     // Caches
 765     //
 766     params->icacheInterface = icache ? icache->getInterface() : NULL;
 767     params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
 768     params->cachePorts = cachePorts;
 769
 770     params->width = width;
 771     params->frontEndWidth = frontEndWidth;
 772     params->backEndWidth = backEndWidth;
 773     params->backEndSquashLatency = backEndSquashLatency;
 774     params->backEndLatency = backEndLatency;
 775     params->maxInstBufferSize = maxInstBufferSize;
 776     params->numPhysicalRegs = numPhysIntRegs + numPhysFloatRegs;
 777
 778     params->decodeToFetchDelay = decodeToFetchDelay;
 779     params->renameToFetchDelay = renameToFetchDelay;
 780     params->iewToFetchDelay = iewToFetchDelay;
 781     params->commitToFetchDelay = commitToFetchDelay;
 782     params->fetchWidth = fetchWidth;
 783
 784     params->renameToDecodeDelay = renameToDecodeDelay;
 785     params->iewToDecodeDelay = iewToDecodeDelay;
 786     params->commitToDecodeDelay = commitToDecodeDelay;
 787     params->fetchToDecodeDelay = fetchToDecodeDelay;
 788     params->decodeWidth = decodeWidth;
 789
 790     params->iewToRenameDelay = iewToRenameDelay;
 791     params->commitToRenameDelay = commitToRenameDelay;
 792     params->decodeToRenameDelay = decodeToRenameDelay;
 793     params->renameWidth = renameWidth;
 794
 795     params->commitToIEWDelay = commitToIEWDelay;
 796     params->renameToIEWDelay = renameToIEWDelay;
 797     params->issueToExecuteDelay = issueToExecuteDelay;
 798     params->issueWidth = issueWidth;
 799     params->executeWidth = executeWidth;
 800     params->executeIntWidth = executeIntWidth;
 801     params->executeFloatWidth = executeFloatWidth;
 802     params->executeBranchWidth = executeBranchWidth;
 803     params->executeMemoryWidth = executeMemoryWidth;
 804
 805     params->iewToCommitDelay = iewToCommitDelay;
 806     params->renameToROBDelay = renameToROBDelay;
 807     params->commitWidth = commitWidth;
 808     params->squashWidth = squashWidth;
 809
 810     params->predType = predType;
 811     params->localPredictorSize = localPredictorSize;
 812     params->localCtrBits = localCtrBits;
 813     params->localHistoryTableSize = localHistoryTableSize;
 814     params->localHistoryBits = localHistoryBits;
 815     params->globalPredictorSize = globalPredictorSize;
 816     params->globalCtrBits = globalCtrBits;
 817     params->globalHistoryBits = globalHistoryBits;
 818     params->choicePredictorSize = choicePredictorSize;
 819     params->choiceCtrBits = choiceCtrBits;
 820
 821     params->BTBEntries = BTBEntries;
 822     params->BTBTagSize = BTBTagSize;
 823
 824     params->RASSize = RASSize;
 825
 826     params->LQEntries = LQEntries;
 827     params->SQEntries = SQEntries;
 828
 829     params->SSITSize = SSITSize;
 830     params->LFSTSize = LFSTSize;
 831
 832     params->numPhysIntRegs = numPhysIntRegs;
 833     params->numPhysFloatRegs = numPhysFloatRegs;
 834     params->numIQEntries = numIQEntries;
 835     params->numROBEntries = numROBEntries;
 836
 837     params->decoupledFrontEnd = decoupledFrontEnd;
 838     params->dispatchWidth = dispatchWidth;
 839     params->wbWidth = wbWidth;
 840
 841     params->smtNumFetchingThreads = smtNumFetchingThreads;
 842     params->smtFetchPolicy = smtFetchPolicy;
 843     params->smtIQPolicy    = smtIQPolicy;
 844     params->smtLSQPolicy    = smtLSQPolicy;
 845     params->smtLSQThreshold = smtLSQThreshold;
 846     params->smtROBPolicy   = smtROBPolicy;
 847     params->smtROBThreshold = smtROBThreshold;
 848     params->smtCommitPolicy = smtCommitPolicy;
 849
 850     params->instShiftAmt = 2;
 851
 852     params->deferRegistration = defer_registration;
 853
 854     params->functionTrace = function_trace;
 855     params->functionTraceStart = function_trace_start;
 856
 857     cpu = new SimpleOzoneCPU(params);
 858
 859     return cpu;
 860 }
 861
 862 REGISTER_SIM_OBJECT("SimpleOzoneCPU", SimpleOzoneCPU)
 863