O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.
[gem5.git] / src / cpu / ozone / cpu_builder.cc
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31 #include <string>
32
33 #include "cpu/checker/cpu.hh"
34 #include "cpu/ozone/cpu.hh"
35 #include "cpu/ozone/ozone_impl.hh"
36 #include "cpu/ozone/simple_params.hh"
37 #include "cpu/inst_seq.hh"
38 #include "params/DerivOzoneCPU.hh"
39 #include "sim/process.hh"
40 #include "sim/sim_object.hh"
41
42 class DerivOzoneCPU : public OzoneCPU<OzoneImpl>
43 {
44 public:
45 DerivOzoneCPU(SimpleParams *p)
46 : OzoneCPU<OzoneImpl>(p)
47 { }
48 };
49
50
51 ////////////////////////////////////////////////////////////////////////
52 //
53 // OzoneCPU Simulation Object
54 //
55 DerivOzoneCPU *
56 DerivOzoneCPUParams::create()
57 {
58 DerivOzoneCPU *cpu;
59
60 if (FullSystem) {
61 // Full-system only supports a single thread for the moment.
62 ThreadID actual_num_threads = 1;
63 } else {
64 // In non-full-system mode, we infer the number of threads from
65 // the workload if it's not explicitly specified.
66 ThreadID actual_num_threads =
67 numThreads.isValid() ? numThreads : workload.size();
68
69 if (workload.size() == 0) {
70 fatal("Must specify at least one workload!");
71 }
72 }
73
74 SimpleParams *params = new SimpleParams;
75
76 params->clock = clock;
77
78 params->name = name;
79 params->numberOfThreads = actual_num_threads;
80
81 params->itb = itb;
82 params->dtb = dtb;
83
84 params->system = system;
85 params->cpu_id = cpu_id;
86 params->profile = profile;
87 params->do_quiesce = do_quiesce;
88 params->do_checkpoint_insts = do_checkpoint_insts;
89 params->do_statistics_insts = do_statistics_insts;
90 params->workload = workload;
91
92 params->checker = checker;
93 params->max_insts_any_thread = max_insts_any_thread;
94 params->max_insts_all_threads = max_insts_all_threads;
95 params->max_loads_any_thread = max_loads_any_thread;
96 params->max_loads_all_threads = max_loads_all_threads;
97 params->progress_interval = progress_interval;
98
99 //
100 // Caches
101 //
102 // params->icacheInterface = icache ? icache->getInterface() : NULL;
103 // params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
104 params->cachePorts = cachePorts;
105
106 params->width = width;
107 params->frontEndWidth = frontEndWidth;
108 params->frontEndLatency = frontEndLatency;
109 params->backEndWidth = backEndWidth;
110 params->backEndSquashLatency = backEndSquashLatency;
111 params->backEndLatency = backEndLatency;
112 params->maxInstBufferSize = maxInstBufferSize;
113 params->numPhysicalRegs = numPhysIntRegs + numPhysFloatRegs;
114 params->maxOutstandingMemOps = maxOutstandingMemOps;
115
116 params->decodeToFetchDelay = decodeToFetchDelay;
117 params->renameToFetchDelay = renameToFetchDelay;
118 params->iewToFetchDelay = iewToFetchDelay;
119 params->commitToFetchDelay = commitToFetchDelay;
120 params->fetchWidth = fetchWidth;
121
122 params->renameToDecodeDelay = renameToDecodeDelay;
123 params->iewToDecodeDelay = iewToDecodeDelay;
124 params->commitToDecodeDelay = commitToDecodeDelay;
125 params->fetchToDecodeDelay = fetchToDecodeDelay;
126 params->decodeWidth = decodeWidth;
127
128 params->iewToRenameDelay = iewToRenameDelay;
129 params->commitToRenameDelay = commitToRenameDelay;
130 params->decodeToRenameDelay = decodeToRenameDelay;
131 params->renameWidth = renameWidth;
132
133 params->commitToIEWDelay = commitToIEWDelay;
134 params->renameToIEWDelay = renameToIEWDelay;
135 params->issueToExecuteDelay = issueToExecuteDelay;
136 params->issueWidth = issueWidth;
137 params->executeWidth = executeWidth;
138 params->executeIntWidth = executeIntWidth;
139 params->executeFloatWidth = executeFloatWidth;
140 params->executeBranchWidth = executeBranchWidth;
141 params->executeMemoryWidth = executeMemoryWidth;
142
143 params->iewToCommitDelay = iewToCommitDelay;
144 params->renameToROBDelay = renameToROBDelay;
145 params->commitWidth = commitWidth;
146 params->squashWidth = squashWidth;
147
148 params->predType = predType;
149 params->localPredictorSize = localPredictorSize;
150 params->localCtrBits = localCtrBits;
151 params->localHistoryTableSize = localHistoryTableSize;
152 params->localHistoryBits = localHistoryBits;
153 params->globalPredictorSize = globalPredictorSize;
154 params->globalCtrBits = globalCtrBits;
155 params->globalHistoryBits = globalHistoryBits;
156 params->choicePredictorSize = choicePredictorSize;
157 params->choiceCtrBits = choiceCtrBits;
158
159 params->BTBEntries = BTBEntries;
160 params->BTBTagSize = BTBTagSize;
161
162 params->RASSize = RASSize;
163
164 params->LQEntries = LQEntries;
165 params->SQEntries = SQEntries;
166 params->lsqLimits = lsqLimits;
167
168 params->SSITSize = SSITSize;
169 params->LFSTSize = LFSTSize;
170
171 params->numPhysIntRegs = numPhysIntRegs;
172 params->numPhysFloatRegs = numPhysFloatRegs;
173 params->numIQEntries = numIQEntries;
174 params->numROBEntries = numROBEntries;
175
176 params->decoupledFrontEnd = decoupledFrontEnd;
177 params->dispatchWidth = dispatchWidth;
178 params->wbWidth = wbWidth;
179
180 params->smtNumFetchingThreads = smtNumFetchingThreads;
181 params->smtFetchPolicy = smtFetchPolicy;
182 params->smtIQPolicy = smtIQPolicy;
183 params->smtLSQPolicy = smtLSQPolicy;
184 params->smtLSQThreshold = smtLSQThreshold;
185 params->smtROBPolicy = smtROBPolicy;
186 params->smtROBThreshold = smtROBThreshold;
187 params->smtCommitPolicy = smtCommitPolicy;
188
189 params->instShiftAmt = 2;
190
191 params->deferRegistration = defer_registration;
192
193 params->functionTrace = function_trace;
194 params->functionTraceStart = function_trace_start;
195
196 cpu = new DerivOzoneCPU(params);
197
198 return cpu;
199 }