2 * Copyright (c) 2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include "cpu/checker/cpu.hh"
34 #include "cpu/inst_seq.hh"
35 #include "cpu/ozone/cpu.hh"
36 #include "cpu/ozone/ozone_impl.hh"
37 #include "cpu/ozone/simple_params.hh"
38 #include "sim/builder.hh"
39 #include "sim/process.hh"
40 #include "sim/sim_object.hh"
42 class DerivOzoneCPU
: public OzoneCPU
<OzoneImpl
>
45 DerivOzoneCPU(SimpleParams
*p
)
46 : OzoneCPU
<OzoneImpl
>(p
)
51 ////////////////////////////////////////////////////////////////////////
53 // OzoneCPU Simulation Object
56 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU
)
59 Param
<int> numThreads
;
62 SimObjectParam
<System
*> system
;
64 SimObjectParam
<AlphaITB
*> itb
;
65 SimObjectParam
<AlphaDTB
*> dtb
;
67 SimObjectVectorParam
<Process
*> workload
;
68 //SimObjectParam<PageTable *> page_table;
71 SimObjectParam
<MemObject
*> mem
;
73 SimObjectParam
<BaseCPU
*> checker
;
75 Param
<Counter
> max_insts_any_thread
;
76 Param
<Counter
> max_insts_all_threads
;
77 Param
<Counter
> max_loads_any_thread
;
78 Param
<Counter
> max_loads_all_threads
;
80 //SimObjectParam<BaseCache *> icache;
81 //SimObjectParam<BaseCache *> dcache;
83 Param
<unsigned> cachePorts
;
84 Param
<unsigned> width
;
85 Param
<unsigned> frontEndWidth
;
86 Param
<unsigned> backEndWidth
;
87 Param
<unsigned> backEndSquashLatency
;
88 Param
<unsigned> backEndLatency
;
89 Param
<unsigned> maxInstBufferSize
;
90 Param
<unsigned> numPhysicalRegs
;
91 Param
<unsigned> maxOutstandingMemOps
;
93 Param
<unsigned> decodeToFetchDelay
;
94 Param
<unsigned> renameToFetchDelay
;
95 Param
<unsigned> iewToFetchDelay
;
96 Param
<unsigned> commitToFetchDelay
;
97 Param
<unsigned> fetchWidth
;
99 Param
<unsigned> renameToDecodeDelay
;
100 Param
<unsigned> iewToDecodeDelay
;
101 Param
<unsigned> commitToDecodeDelay
;
102 Param
<unsigned> fetchToDecodeDelay
;
103 Param
<unsigned> decodeWidth
;
105 Param
<unsigned> iewToRenameDelay
;
106 Param
<unsigned> commitToRenameDelay
;
107 Param
<unsigned> decodeToRenameDelay
;
108 Param
<unsigned> renameWidth
;
110 Param
<unsigned> commitToIEWDelay
;
111 Param
<unsigned> renameToIEWDelay
;
112 Param
<unsigned> issueToExecuteDelay
;
113 Param
<unsigned> issueWidth
;
114 Param
<unsigned> executeWidth
;
115 Param
<unsigned> executeIntWidth
;
116 Param
<unsigned> executeFloatWidth
;
117 Param
<unsigned> executeBranchWidth
;
118 Param
<unsigned> executeMemoryWidth
;
120 Param
<unsigned> iewToCommitDelay
;
121 Param
<unsigned> renameToROBDelay
;
122 Param
<unsigned> commitWidth
;
123 Param
<unsigned> squashWidth
;
125 Param
<std::string
> predType
;
126 Param
<unsigned> localPredictorSize
;
127 Param
<unsigned> localCtrBits
;
128 Param
<unsigned> localHistoryTableSize
;
129 Param
<unsigned> localHistoryBits
;
130 Param
<unsigned> globalPredictorSize
;
131 Param
<unsigned> globalCtrBits
;
132 Param
<unsigned> globalHistoryBits
;
133 Param
<unsigned> choicePredictorSize
;
134 Param
<unsigned> choiceCtrBits
;
136 Param
<unsigned> BTBEntries
;
137 Param
<unsigned> BTBTagSize
;
139 Param
<unsigned> RASSize
;
141 Param
<unsigned> LQEntries
;
142 Param
<unsigned> SQEntries
;
143 Param
<unsigned> LFSTSize
;
144 Param
<unsigned> SSITSize
;
146 Param
<unsigned> numPhysIntRegs
;
147 Param
<unsigned> numPhysFloatRegs
;
148 Param
<unsigned> numIQEntries
;
149 Param
<unsigned> numROBEntries
;
151 Param
<bool> decoupledFrontEnd
;
152 Param
<int> dispatchWidth
;
155 Param
<unsigned> smtNumFetchingThreads
;
156 Param
<std::string
> smtFetchPolicy
;
157 Param
<std::string
> smtLSQPolicy
;
158 Param
<unsigned> smtLSQThreshold
;
159 Param
<std::string
> smtIQPolicy
;
160 Param
<unsigned> smtIQThreshold
;
161 Param
<std::string
> smtROBPolicy
;
162 Param
<unsigned> smtROBThreshold
;
163 Param
<std::string
> smtCommitPolicy
;
165 Param
<unsigned> instShiftAmt
;
167 Param
<bool> defer_registration
;
169 Param
<bool> function_trace
;
170 Param
<Tick
> function_trace_start
;
172 END_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU
)
174 BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU
)
176 INIT_PARAM(clock
, "clock speed"),
177 INIT_PARAM(numThreads
, "number of HW thread contexts"),
180 INIT_PARAM(system
, "System object"),
181 INIT_PARAM(cpu_id
, "processor ID"),
182 INIT_PARAM(itb
, "Instruction translation buffer"),
183 INIT_PARAM(dtb
, "Data translation buffer"),
185 INIT_PARAM(workload
, "Processes to run"),
186 // INIT_PARAM(page_table, "Page table"),
187 #endif // FULL_SYSTEM
189 INIT_PARAM_DFLT(mem
, "Memory", NULL
),
191 INIT_PARAM_DFLT(checker
, "Checker CPU", NULL
),
193 INIT_PARAM_DFLT(max_insts_any_thread
,
194 "Terminate when any thread reaches this inst count",
196 INIT_PARAM_DFLT(max_insts_all_threads
,
197 "Terminate when all threads have reached"
200 INIT_PARAM_DFLT(max_loads_any_thread
,
201 "Terminate when any thread reaches this load count",
203 INIT_PARAM_DFLT(max_loads_all_threads
,
204 "Terminate when all threads have reached this load"
208 // INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
209 // INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
211 INIT_PARAM_DFLT(cachePorts
, "Cache Ports", 200),
212 INIT_PARAM_DFLT(width
, "Width", 1),
213 INIT_PARAM_DFLT(frontEndWidth
, "Front end width", 1),
214 INIT_PARAM_DFLT(backEndWidth
, "Back end width", 1),
215 INIT_PARAM_DFLT(backEndSquashLatency
, "Back end squash latency", 1),
216 INIT_PARAM_DFLT(backEndLatency
, "Back end latency", 1),
217 INIT_PARAM_DFLT(maxInstBufferSize
, "Maximum instruction buffer size", 16),
218 INIT_PARAM(numPhysicalRegs
, "Number of physical registers"),
219 INIT_PARAM_DFLT(maxOutstandingMemOps
, "Maximum outstanding memory operations", 4),
221 INIT_PARAM(decodeToFetchDelay
, "Decode to fetch delay"),
222 INIT_PARAM(renameToFetchDelay
, "Rename to fetch delay"),
223 INIT_PARAM(iewToFetchDelay
, "Issue/Execute/Writeback to fetch"
225 INIT_PARAM(commitToFetchDelay
, "Commit to fetch delay"),
226 INIT_PARAM(fetchWidth
, "Fetch width"),
227 INIT_PARAM(renameToDecodeDelay
, "Rename to decode delay"),
228 INIT_PARAM(iewToDecodeDelay
, "Issue/Execute/Writeback to decode"
230 INIT_PARAM(commitToDecodeDelay
, "Commit to decode delay"),
231 INIT_PARAM(fetchToDecodeDelay
, "Fetch to decode delay"),
232 INIT_PARAM(decodeWidth
, "Decode width"),
234 INIT_PARAM(iewToRenameDelay
, "Issue/Execute/Writeback to rename"
236 INIT_PARAM(commitToRenameDelay
, "Commit to rename delay"),
237 INIT_PARAM(decodeToRenameDelay
, "Decode to rename delay"),
238 INIT_PARAM(renameWidth
, "Rename width"),
240 INIT_PARAM(commitToIEWDelay
, "Commit to "
241 "Issue/Execute/Writeback delay"),
242 INIT_PARAM(renameToIEWDelay
, "Rename to "
243 "Issue/Execute/Writeback delay"),
244 INIT_PARAM(issueToExecuteDelay
, "Issue to execute delay (internal"
245 "to the IEW stage)"),
246 INIT_PARAM(issueWidth
, "Issue width"),
247 INIT_PARAM(executeWidth
, "Execute width"),
248 INIT_PARAM(executeIntWidth
, "Integer execute width"),
249 INIT_PARAM(executeFloatWidth
, "Floating point execute width"),
250 INIT_PARAM(executeBranchWidth
, "Branch execute width"),
251 INIT_PARAM(executeMemoryWidth
, "Memory execute width"),
253 INIT_PARAM(iewToCommitDelay
, "Issue/Execute/Writeback to commit "
255 INIT_PARAM(renameToROBDelay
, "Rename to reorder buffer delay"),
256 INIT_PARAM(commitWidth
, "Commit width"),
257 INIT_PARAM(squashWidth
, "Squash width"),
259 INIT_PARAM(predType
, "Type of branch predictor ('local', 'tournament')"),
260 INIT_PARAM(localPredictorSize
, "Size of local predictor"),
261 INIT_PARAM(localCtrBits
, "Bits per counter"),
262 INIT_PARAM(localHistoryTableSize
, "Size of local history table"),
263 INIT_PARAM(localHistoryBits
, "Bits for the local history"),
264 INIT_PARAM(globalPredictorSize
, "Size of global predictor"),
265 INIT_PARAM(globalCtrBits
, "Bits per counter"),
266 INIT_PARAM(globalHistoryBits
, "Bits of history"),
267 INIT_PARAM(choicePredictorSize
, "Size of choice predictor"),
268 INIT_PARAM(choiceCtrBits
, "Bits of choice counters"),
270 INIT_PARAM(BTBEntries
, "Number of BTB entries"),
271 INIT_PARAM(BTBTagSize
, "Size of the BTB tags, in bits"),
273 INIT_PARAM(RASSize
, "RAS size"),
275 INIT_PARAM(LQEntries
, "Number of load queue entries"),
276 INIT_PARAM(SQEntries
, "Number of store queue entries"),
277 INIT_PARAM(LFSTSize
, "Last fetched store table size"),
278 INIT_PARAM(SSITSize
, "Store set ID table size"),
280 INIT_PARAM(numPhysIntRegs
, "Number of physical integer registers"),
281 INIT_PARAM(numPhysFloatRegs
, "Number of physical floating point "
283 INIT_PARAM(numIQEntries
, "Number of instruction queue entries"),
284 INIT_PARAM(numROBEntries
, "Number of reorder buffer entries"),
286 INIT_PARAM_DFLT(decoupledFrontEnd
, "Decoupled front end", true),
287 INIT_PARAM_DFLT(dispatchWidth
, "Dispatch width", 0),
288 INIT_PARAM_DFLT(wbWidth
, "Writeback width", 0),
290 INIT_PARAM_DFLT(smtNumFetchingThreads
, "SMT Number of Fetching Threads", 1),
291 INIT_PARAM_DFLT(smtFetchPolicy
, "SMT Fetch Policy", "SingleThread"),
292 INIT_PARAM_DFLT(smtLSQPolicy
, "SMT LSQ Sharing Policy", "Partitioned"),
293 INIT_PARAM_DFLT(smtLSQThreshold
,"SMT LSQ Threshold", 100),
294 INIT_PARAM_DFLT(smtIQPolicy
, "SMT IQ Policy", "Partitioned"),
295 INIT_PARAM_DFLT(smtIQThreshold
, "SMT IQ Threshold", 100),
296 INIT_PARAM_DFLT(smtROBPolicy
, "SMT ROB Sharing Policy", "Partitioned"),
297 INIT_PARAM_DFLT(smtROBThreshold
,"SMT ROB Threshold", 100),
298 INIT_PARAM_DFLT(smtCommitPolicy
,"SMT Commit Fetch Policy", "RoundRobin"),
300 INIT_PARAM(instShiftAmt
, "Number of bits to shift instructions by"),
301 INIT_PARAM(defer_registration
, "defer system registration (for sampling)"),
303 INIT_PARAM(function_trace
, "Enable function trace"),
304 INIT_PARAM(function_trace_start
, "Cycle to start function trace")
306 END_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU
)
308 CREATE_SIM_OBJECT(DerivOzoneCPU
)
313 // Full-system only supports a single thread for the moment.
314 int actual_num_threads
= 1;
316 // In non-full-system mode, we infer the number of threads from
317 // the workload if it's not explicitly specified.
318 int actual_num_threads
=
319 numThreads
.isValid() ? numThreads
: workload
.size();
321 if (workload
.size() == 0) {
322 fatal("Must specify at least one workload!");
327 SimpleParams
*params
= new SimpleParams
;
329 params
->clock
= clock
;
331 params
->name
= getInstanceName();
332 params
->numberOfThreads
= actual_num_threads
;
335 params
->system
= system
;
336 params
->cpu_id
= cpu_id
;
340 params
->workload
= workload
;
341 // params->pTable = page_table;
342 #endif // FULL_SYSTEM
345 params
->checker
= checker
;
346 params
->max_insts_any_thread
= max_insts_any_thread
;
347 params
->max_insts_all_threads
= max_insts_all_threads
;
348 params
->max_loads_any_thread
= max_loads_any_thread
;
349 params
->max_loads_all_threads
= max_loads_all_threads
;
354 // params->icacheInterface = icache ? icache->getInterface() : NULL;
355 // params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
356 params
->cachePorts
= cachePorts
;
358 params
->width
= width
;
359 params
->frontEndWidth
= frontEndWidth
;
360 params
->backEndWidth
= backEndWidth
;
361 params
->backEndSquashLatency
= backEndSquashLatency
;
362 params
->backEndLatency
= backEndLatency
;
363 params
->maxInstBufferSize
= maxInstBufferSize
;
364 params
->numPhysicalRegs
= numPhysIntRegs
+ numPhysFloatRegs
;
365 params
->maxOutstandingMemOps
= maxOutstandingMemOps
;
367 params
->decodeToFetchDelay
= decodeToFetchDelay
;
368 params
->renameToFetchDelay
= renameToFetchDelay
;
369 params
->iewToFetchDelay
= iewToFetchDelay
;
370 params
->commitToFetchDelay
= commitToFetchDelay
;
371 params
->fetchWidth
= fetchWidth
;
373 params
->renameToDecodeDelay
= renameToDecodeDelay
;
374 params
->iewToDecodeDelay
= iewToDecodeDelay
;
375 params
->commitToDecodeDelay
= commitToDecodeDelay
;
376 params
->fetchToDecodeDelay
= fetchToDecodeDelay
;
377 params
->decodeWidth
= decodeWidth
;
379 params
->iewToRenameDelay
= iewToRenameDelay
;
380 params
->commitToRenameDelay
= commitToRenameDelay
;
381 params
->decodeToRenameDelay
= decodeToRenameDelay
;
382 params
->renameWidth
= renameWidth
;
384 params
->commitToIEWDelay
= commitToIEWDelay
;
385 params
->renameToIEWDelay
= renameToIEWDelay
;
386 params
->issueToExecuteDelay
= issueToExecuteDelay
;
387 params
->issueWidth
= issueWidth
;
388 params
->executeWidth
= executeWidth
;
389 params
->executeIntWidth
= executeIntWidth
;
390 params
->executeFloatWidth
= executeFloatWidth
;
391 params
->executeBranchWidth
= executeBranchWidth
;
392 params
->executeMemoryWidth
= executeMemoryWidth
;
394 params
->iewToCommitDelay
= iewToCommitDelay
;
395 params
->renameToROBDelay
= renameToROBDelay
;
396 params
->commitWidth
= commitWidth
;
397 params
->squashWidth
= squashWidth
;
399 params
->predType
= predType
;
400 params
->localPredictorSize
= localPredictorSize
;
401 params
->localCtrBits
= localCtrBits
;
402 params
->localHistoryTableSize
= localHistoryTableSize
;
403 params
->localHistoryBits
= localHistoryBits
;
404 params
->globalPredictorSize
= globalPredictorSize
;
405 params
->globalCtrBits
= globalCtrBits
;
406 params
->globalHistoryBits
= globalHistoryBits
;
407 params
->choicePredictorSize
= choicePredictorSize
;
408 params
->choiceCtrBits
= choiceCtrBits
;
410 params
->BTBEntries
= BTBEntries
;
411 params
->BTBTagSize
= BTBTagSize
;
413 params
->RASSize
= RASSize
;
415 params
->LQEntries
= LQEntries
;
416 params
->SQEntries
= SQEntries
;
418 params
->SSITSize
= SSITSize
;
419 params
->LFSTSize
= LFSTSize
;
421 params
->numPhysIntRegs
= numPhysIntRegs
;
422 params
->numPhysFloatRegs
= numPhysFloatRegs
;
423 params
->numIQEntries
= numIQEntries
;
424 params
->numROBEntries
= numROBEntries
;
426 params
->decoupledFrontEnd
= decoupledFrontEnd
;
427 params
->dispatchWidth
= dispatchWidth
;
428 params
->wbWidth
= wbWidth
;
430 params
->smtNumFetchingThreads
= smtNumFetchingThreads
;
431 params
->smtFetchPolicy
= smtFetchPolicy
;
432 params
->smtIQPolicy
= smtIQPolicy
;
433 params
->smtLSQPolicy
= smtLSQPolicy
;
434 params
->smtLSQThreshold
= smtLSQThreshold
;
435 params
->smtROBPolicy
= smtROBPolicy
;
436 params
->smtROBThreshold
= smtROBThreshold
;
437 params
->smtCommitPolicy
= smtCommitPolicy
;
439 params
->instShiftAmt
= 2;
441 params
->deferRegistration
= defer_registration
;
443 params
->functionTrace
= function_trace
;
444 params
->functionTraceStart
= function_trace_start
;
446 cpu
= new DerivOzoneCPU(params
);
451 REGISTER_SIM_OBJECT("DerivOzoneCPU", DerivOzoneCPU
)