2 * Copyright (c) 2006 The Regents of The University of Michigan
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32 #include "config/full_system.hh"
33 #include "config/use_checker.hh"
35 #include "arch/isa_traits.hh" // For MachInst
36 #include "base/trace.hh"
37 #include "cpu/base.hh"
38 #include "cpu/simple_thread.hh"
39 #include "cpu/thread_context.hh"
40 #include "cpu/exetrace.hh"
41 #include "cpu/ozone/cpu.hh"
42 #include "cpu/quiesce_event.hh"
43 #include "cpu/static_inst.hh"
44 #include "sim/sim_object.hh"
45 #include "sim/stats.hh"
48 #include "arch/faults.hh"
49 #include "arch/alpha/osfpal.hh"
50 #include "arch/tlb.hh"
51 #include "arch/types.hh"
52 #include "arch/kernel_stats.hh"
53 #include "arch/vtophys.hh"
54 #include "base/callback.hh"
55 #include "cpu/profile.hh"
56 #include "mem/physical.hh"
57 #include "sim/faults.hh"
58 #include "sim/sim_events.hh"
59 #include "sim/sim_exit.hh"
60 #include "sim/system.hh"
62 #include "sim/process.hh"
66 #include "cpu/checker/thread_context.hh"
69 using namespace TheISA;
72 OzoneCPU<Impl>::TickEvent::TickEvent(OzoneCPU *c, int w)
73 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
79 OzoneCPU<Impl>::TickEvent::process()
86 OzoneCPU<Impl>::TickEvent::description()
88 return "OzoneCPU tick event";
92 OzoneCPU<Impl>::OzoneCPU(Params *p)
94 : BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
96 : BaseCPU(p), thread(this, 0, p->workload[0], 0),
97 tickEvent(this, p->width),
101 frontEnd = new FrontEnd(p);
102 backEnd = new BackEnd(p);
108 BaseCPU *temp_checker = p->checker;
109 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
111 checker->setSystem(p->system);
113 checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
114 thread.tc = checkerTC;
117 panic("Checker enabled but not compiled in!");
120 // If checker is not being used, then the xcProxy points
121 // directly to the CPU's ExecContext.
123 thread.tc = &ozoneTC;
128 ozoneTC.thread = &thread;
130 thread.inSyscall = false;
132 thread.setStatus(ThreadContext::Suspended);
134 // Setup thread state stuff.
138 thread.quiesceEvent = new EndQuiesceEvent(tc);
143 physmem = p->system->physmem;
146 thread.profile = new FunctionProfile(p->system->kernelSymtab);
147 // @todo: This might be better as an ThreadContext instead of OzoneTC
149 new MakeCallback<OzoneTC,
150 &OzoneTC::dumpFuncProfile>(&ozoneTC);
151 registerExitCallback(cb);
154 // let's fill with a dummy node for now so we don't get a segfault
155 // on the first cycle when there's no node available.
156 static ProfileNode dummyNode;
157 thread.profileNode = &dummyNode;
158 thread.profilePC = 3;
161 #endif // !FULL_SYSTEM
166 threadContexts.push_back(tc);
168 frontEnd->setCPU(this);
169 backEnd->setCPU(this);
174 frontEnd->setThreadState(&thread);
175 backEnd->setThreadState(&thread);
177 frontEnd->setCommBuffer(&comm);
178 backEnd->setCommBuffer(&comm);
180 frontEnd->setBackEnd(backEnd);
181 backEnd->setFrontEnd(frontEnd);
187 // Setup rename table, initializing all values to ready.
188 for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
189 thread.renameTable[i] = new DynInst(this);
190 thread.renameTable[i]->setResultReady();
193 frontEnd->renameTable.copyFrom(thread.renameTable);
194 backEnd->renameTable.copyFrom(thread.renameTable);
198 FunctionalPort *phys_port;
199 VirtualPort *virt_port;
200 phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
202 mem_port = system->physmem->getPort("functional");
203 mem_port->setPeer(phys_port);
204 phys_port->setPeer(mem_port);
206 virt_port = new VirtualPort(csprintf("%s-%d-vport",
208 mem_port = system->physmem->getPort("functional");
209 mem_port->setPeer(virt_port);
210 virt_port->setPeer(mem_port);
212 thread.setPhysPort(phys_port);
213 thread.setVirtPort(virt_port);
216 DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
219 template <class Impl>
220 OzoneCPU<Impl>::~OzoneCPU()
224 template <class Impl>
226 OzoneCPU<Impl>::switchOut()
228 BaseCPU::switchOut();
230 // Front end needs state from back end, so switch out the back end first.
231 backEnd->switchOut();
232 frontEnd->switchOut();
235 template <class Impl>
237 OzoneCPU<Impl>::signalSwitched()
239 // Only complete the switchout when both the front end and back
240 // end have signalled they are ready to switch.
241 if (++switchCount == 2) {
242 backEnd->doSwitchOut();
243 frontEnd->doSwitchOut();
246 checker->switchOut();
249 _status = SwitchedOut;
251 // Loop through all registers
252 for (int i = 0; i < AlphaISA::TotalNumRegs; ++i) {
253 assert(thread.renameTable[i] == frontEnd->renameTable[i]);
255 assert(thread.renameTable[i] == backEnd->renameTable[i]);
257 DPRINTF(OzoneCPU, "Checking if register %i matches.\n", i);
261 if (tickEvent.scheduled())
264 assert(switchCount <= 2);
267 template <class Impl>
269 OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
271 BaseCPU::takeOverFrom(oldCPU);
273 thread.trapPending = false;
274 thread.inSyscall = false;
276 backEnd->takeOverFrom();
277 frontEnd->takeOverFrom();
278 frontEnd->renameTable.copyFrom(thread.renameTable);
279 backEnd->renameTable.copyFrom(thread.renameTable);
280 assert(!tickEvent.scheduled());
283 // Check rename table.
284 for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
285 assert(thread.renameTable[i]->isResultReady());
289 // @todo: Fix hardcoded number
290 // Clear out any old information in time buffer.
291 for (int i = 0; i < 15; ++i) {
295 // if any of this CPU's ThreadContexts are active, mark the CPU as
296 // running and schedule its tick event.
297 for (int i = 0; i < threadContexts.size(); ++i) {
298 ThreadContext *tc = threadContexts[i];
299 if (tc->status() == ThreadContext::Active &&
300 _status != Running) {
302 tickEvent.schedule(curTick);
305 // Nothing running, change status to reflect that we're no longer
307 if (_status == SwitchedOut) {
312 template <class Impl>
314 OzoneCPU<Impl>::activateContext(int thread_num, int delay)
316 // Eventually change this in SMT.
317 assert(thread_num == 0);
319 assert(_status == Idle);
321 scheduleTickEvent(delay);
324 if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
325 thread.quiesceEvent->deschedule();
327 thread.setStatus(ThreadContext::Active);
328 frontEnd->wakeFromQuiesce();
331 template <class Impl>
333 OzoneCPU<Impl>::suspendContext(int thread_num)
335 // Eventually change this in SMT.
336 assert(thread_num == 0);
337 // @todo: Figure out how to initially set the status properly so
339 // assert(_status == Running);
341 unscheduleTickEvent();
345 template <class Impl>
347 OzoneCPU<Impl>::deallocateContext(int thread_num, int delay)
349 // for now, these are equivalent
350 suspendContext(thread_num);
353 template <class Impl>
355 OzoneCPU<Impl>::haltContext(int thread_num)
357 // for now, these are equivalent
358 suspendContext(thread_num);
361 template <class Impl>
363 OzoneCPU<Impl>::regStats()
365 using namespace Stats;
370 .name(name() + ".num_insts")
371 .desc("Number of instructions executed")
375 .name(name() + ".num_refs")
376 .desc("Number of memory references")
380 .name(name() + ".not_idle_fraction")
381 .desc("Percentage of non-idle cycles")
385 .name(name() + ".idle_fraction")
386 .desc("Percentage of idle cycles")
390 .name(name() + ".quiesce_cycles")
391 .desc("Number of cycles spent in quiesce")
394 idleFraction = constant(1.0) - notIdleFraction;
396 frontEnd->regStats();
400 template <class Impl>
402 OzoneCPU<Impl>::resetStats()
404 // startNumInst = numInst;
405 notIdleFraction = (_status != Idle);
408 template <class Impl>
410 OzoneCPU<Impl>::init()
414 // Mark this as in syscall so it won't need to squash
415 thread.inSyscall = true;
417 for (int i = 0; i < threadContexts.size(); ++i) {
418 ThreadContext *tc = threadContexts[i];
420 // initialize CPU, including PC
421 TheISA::initCPU(tc, tc->readCpuId());
424 frontEnd->renameTable.copyFrom(thread.renameTable);
425 backEnd->renameTable.copyFrom(thread.renameTable);
427 thread.inSyscall = false;
430 template <class Impl>
432 OzoneCPU<Impl>::getPort(const std::string &if_name, int idx)
434 if (if_name == "dcache_port")
435 return backEnd->getDcachePort();
436 else if (if_name == "icache_port")
437 return frontEnd->getIcachePort();
439 panic("No Such Port\n");
442 template <class Impl>
444 OzoneCPU<Impl>::serialize(std::ostream &os)
446 BaseCPU::serialize(os);
447 SERIALIZE_ENUM(_status);
448 nameOut(os, csprintf("%s.tc", name()));
449 ozoneTC.serialize(os);
450 nameOut(os, csprintf("%s.tickEvent", name()));
451 tickEvent.serialize(os);
453 // Use SimpleThread's ability to checkpoint to make it easier to
454 // write out the registers. Also make this static so it doesn't
455 // get instantiated multiple times (causes a panic in statistics).
456 static SimpleThread temp;
458 nameOut(os, csprintf("%s.xc.0", name()));
459 temp.copyTC(thread.getTC());
463 template <class Impl>
465 OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
467 BaseCPU::unserialize(cp, section);
468 UNSERIALIZE_ENUM(_status);
469 ozoneTC.unserialize(cp, csprintf("%s.tc", section));
470 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
472 // Use SimpleThread's ability to checkpoint to make it easier to
473 // read in the registers. Also make this static so it doesn't
474 // get instantiated multiple times (causes a panic in statistics).
475 static SimpleThread temp;
477 temp.copyTC(thread.getTC());
478 temp.unserialize(cp, csprintf("%s.xc.0", section));
479 thread.getTC()->copyArchRegs(temp.getTC());
482 template <class Impl>
484 OzoneCPU<Impl>::copySrcTranslate(Addr src)
486 panic("Copy not implemented!\n");
489 static bool no_warn = true;
490 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
491 // Only support block sizes of 64 atm.
492 assert(blk_size == 64);
493 int offset = src & (blk_size - 1);
495 // Make sure block doesn't span page
497 (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
498 (src >> 40) != 0xfffffc) {
499 warn("Copied block source spans pages %x.", src);
503 memReq->reset(src & ~(blk_size - 1), blk_size);
505 // translate to physical address
506 Fault fault = tc->translateDataReadReq(memReq);
508 assert(fault != Alignment_Fault);
510 if (fault == NoFault) {
511 tc->copySrcAddr = src;
512 tc->copySrcPhysAddr = memReq->paddr + offset;
515 tc->copySrcPhysAddr = 0;
521 template <class Impl>
523 OzoneCPU<Impl>::copy(Addr dest)
525 panic("Copy not implemented!\n");
528 static bool no_warn = true;
529 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
530 // Only support block sizes of 64 atm.
531 assert(blk_size == 64);
532 uint8_t data[blk_size];
533 //assert(tc->copySrcAddr);
534 int offset = dest & (blk_size - 1);
536 // Make sure block doesn't span page
538 (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
539 (dest >> 40) != 0xfffffc) {
541 warn("Copied block destination spans pages %x. ", dest);
544 memReq->reset(dest & ~(blk_size -1), blk_size);
545 // translate to physical address
546 Fault fault = tc->translateDataWriteReq(memReq);
548 assert(fault != Alignment_Fault);
550 if (fault == NoFault) {
551 Addr dest_addr = memReq->paddr + offset;
552 // Need to read straight from memory since we have more than 8 bytes.
553 memReq->paddr = tc->copySrcPhysAddr;
554 tc->mem->read(memReq, data);
555 memReq->paddr = dest_addr;
556 tc->mem->write(memReq, data);
557 if (dcacheInterface) {
559 memReq->completionEvent = NULL;
560 memReq->paddr = tc->copySrcPhysAddr;
561 memReq->dest = dest_addr;
563 memReq->time = curTick;
564 dcacheInterface->access(memReq);
572 template <class Impl>
574 OzoneCPU<Impl>::dbg_vtophys(Addr addr)
576 return vtophys(tc, addr);
578 #endif // FULL_SYSTEM
581 template <class Impl>
583 OzoneCPU<Impl>::post_interrupt(int int_num, int index)
585 BaseCPU::post_interrupt(int_num, index);
587 if (_status == Idle) {
588 DPRINTF(IPI,"Suspended Processor awoke\n");
589 // thread.activate();
590 // Hack for now. Otherwise might have to go through the tc, or
591 // I need to figure out what's the right thing to call.
592 activateContext(thread.readTid(), 1);
595 #endif // FULL_SYSTEM
597 /* start simulation, program loaded, processor precise state initialized */
598 template <class Impl>
600 OzoneCPU<Impl>::tick()
602 DPRINTF(OzoneCPU, "\n\nOzoneCPU: Ticking cpu.\n");
605 thread.renameTable[ZeroReg]->setIntResult(0);
606 thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
607 setDoubleResult(0.0);
613 // check for instruction-count-based events
614 comInstEventQueue[0]->serviceEvents(numInst);
616 if (!tickEvent.scheduled() && _status == Running)
617 tickEvent.schedule(curTick + cycles(1));
620 template <class Impl>
622 OzoneCPU<Impl>::squashFromTC()
624 thread.inSyscall = true;
625 backEnd->generateTCEvent();
629 template <class Impl>
631 OzoneCPU<Impl>::syscall(uint64_t &callnum)
633 // Not sure this copy is needed, depending on how the TC proxy is made.
634 thread.renameTable.copyFrom(backEnd->renameTable);
636 thread.inSyscall = true;
638 thread.funcExeInst++;
640 DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst);
642 thread.process->syscall(callnum, tc);
644 thread.funcExeInst--;
646 thread.inSyscall = false;
648 frontEnd->renameTable.copyFrom(thread.renameTable);
649 backEnd->renameTable.copyFrom(thread.renameTable);
652 template <class Impl>
654 OzoneCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
656 // check for error condition. Alpha syscall convention is to
657 // indicate success/failure in reg a3 (r19) and put the
658 // return value itself in the standard return value reg (v0).
659 if (return_value.successful()) {
661 thread.renameTable[SyscallSuccessReg]->setIntResult(0);
662 thread.renameTable[ReturnValueReg]->setIntResult(
663 return_value.value());
665 // got an error, return details
666 thread.renameTable[SyscallSuccessReg]->setIntResult((IntReg) -1);
667 thread.renameTable[ReturnValueReg]->setIntResult(
668 -return_value.value());
672 template <class Impl>
674 OzoneCPU<Impl>::hwrei()
676 // Need to move this to ISA code
677 // May also need to make this per thread
680 lockAddrList.clear();
681 thread.kernelStats->hwrei();
683 // FIXME: XXX check for interrupts? XXX
687 template <class Impl>
689 OzoneCPU<Impl>::processInterrupts()
691 // Check for interrupts here. For now can copy the code that
692 // exists within isa_fullsys_traits.hh. Also assume that thread 0
693 // is the one that handles the interrupts.
695 // Check if there are any outstanding interrupts
696 //Handle the interrupts
697 Fault interrupt = this->interrupts.getInterrupt(thread.getTC());
699 if (interrupt != NoFault) {
700 this->interrupts.updateIntrInfo(thread.getTC());
701 interrupt->invoke(thread.getTC());
705 template <class Impl>
707 OzoneCPU<Impl>::simPalCheck(int palFunc)
709 // Need to move this to ISA code
710 // May also need to make this per thread
711 thread.kernelStats->callpal(palFunc, tc);
715 haltContext(thread.readTid());
716 if (--System::numSystemsRunning == 0)
717 exitSimLoop("all cpus halted");
722 if (system->breakpoint())
731 template <class Impl>
733 OzoneCPU<Impl>::OzoneTC::getCpuPtr()
738 template <class Impl>
740 OzoneCPU<Impl>::OzoneTC::setCpuId(int id)
743 thread->setCpuId(id);
747 template <class Impl>
749 OzoneCPU<Impl>::OzoneTC::delVirtPort(VirtualPort *vp)
751 delete vp->getPeer();
756 template <class Impl>
758 OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
760 thread->setStatus(new_status);
763 template <class Impl>
765 OzoneCPU<Impl>::OzoneTC::activate(int delay)
767 cpu->activateContext(thread->readTid(), delay);
770 /// Set the status to Suspended.
771 template <class Impl>
773 OzoneCPU<Impl>::OzoneTC::suspend()
775 cpu->suspendContext(thread->readTid());
778 /// Set the status to Unallocated.
779 template <class Impl>
781 OzoneCPU<Impl>::OzoneTC::deallocate(int delay)
783 cpu->deallocateContext(thread->readTid(), delay);
786 /// Set the status to Halted.
787 template <class Impl>
789 OzoneCPU<Impl>::OzoneTC::halt()
791 cpu->haltContext(thread->readTid());
795 template <class Impl>
797 OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
799 thread->dumpFuncProfile();
803 template <class Impl>
805 OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
807 // some things should already be set up
809 assert(getSystemPtr() == old_context->getSystemPtr());
811 assert(getProcessPtr() == old_context->getProcessPtr());
814 // copy over functional state
815 setStatus(old_context->status());
816 copyArchRegs(old_context);
817 setCpuId(old_context->readCpuId());
819 thread->setInst(old_context->getInst());
821 setFuncExeInst(old_context->readFuncExeInst());
823 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
825 // Point the quiesce event's TC at this TC so that it wakes up
827 other_quiesce->tc = this;
829 if (thread->quiesceEvent) {
830 thread->quiesceEvent->tc = this;
833 // Copy kernel stats pointer from old context.
834 thread->kernelStats = old_context->getKernelStats();
835 // storeCondFailures = 0;
836 cpu->lockFlag = false;
839 old_context->setStatus(ThreadContext::Unallocated);
842 template <class Impl>
844 OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
847 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
848 thread->kernelStats->regStats(name + ".kern");
852 template <class Impl>
854 OzoneCPU<Impl>::OzoneTC::serialize(std::ostream &os)
856 // Once serialization is added, serialize the quiesce event and
857 // kernel stats. Will need to make sure there aren't multiple
858 // things that serialize them.
861 template <class Impl>
863 OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string §ion)
867 template <class Impl>
869 OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
871 return thread->quiesceEvent;
874 template <class Impl>
876 OzoneCPU<Impl>::OzoneTC::readLastActivate()
878 return thread->lastActivate;
881 template <class Impl>
883 OzoneCPU<Impl>::OzoneTC::readLastSuspend()
885 return thread->lastSuspend;
888 template <class Impl>
890 OzoneCPU<Impl>::OzoneTC::profileClear()
892 thread->profileClear();
895 template <class Impl>
897 OzoneCPU<Impl>::OzoneTC::profileSample()
899 thread->profileSample();
903 template <class Impl>
905 OzoneCPU<Impl>::OzoneTC::getThreadNum()
907 return thread->readTid();
910 template <class Impl>
912 OzoneCPU<Impl>::OzoneTC::getInst()
914 return thread->getInst();
917 template <class Impl>
919 OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
921 thread->PC = tc->readPC();
922 thread->nextPC = tc->readNextPC();
924 cpu->frontEnd->setPC(thread->PC);
925 cpu->frontEnd->setNextPC(thread->nextPC);
927 // First loop through the integer registers.
928 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
929 /* DPRINTF(OzoneCPU, "Copying over register %i, had data %lli, "
930 "now has data %lli.\n",
931 i, thread->renameTable[i]->readIntResult(),
934 thread->renameTable[i]->setIntResult(tc->readIntReg(i));
937 // Then loop through the floating point registers.
938 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
939 int fp_idx = i + TheISA::FP_Base_DepTag;
940 thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
944 thread->funcExeInst = tc->readFuncExeInst();
947 // Need to copy the TC values into the current rename table,
948 // copy the misc regs.
949 copyMiscRegs(tc, this);
952 template <class Impl>
954 OzoneCPU<Impl>::OzoneTC::clearArchRegs()
956 panic("Unimplemented!");
959 template <class Impl>
961 OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx)
963 return thread->renameTable[reg_idx]->readIntResult();
966 template <class Impl>
968 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width)
970 int idx = reg_idx + TheISA::FP_Base_DepTag;
973 return thread->renameTable[idx]->readFloatResult();
975 return thread->renameTable[idx]->readDoubleResult();
977 panic("Unsupported width!");
982 template <class Impl>
984 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
986 int idx = reg_idx + TheISA::FP_Base_DepTag;
987 return thread->renameTable[idx]->readFloatResult();
990 template <class Impl>
992 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width)
994 int idx = reg_idx + TheISA::FP_Base_DepTag;
995 return thread->renameTable[idx]->readIntResult();
998 template <class Impl>
1000 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
1002 int idx = reg_idx + TheISA::FP_Base_DepTag;
1003 return thread->renameTable[idx]->readIntResult();
1006 template <class Impl>
1008 OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
1010 thread->renameTable[reg_idx]->setIntResult(val);
1012 if (!thread->inSyscall) {
1013 cpu->squashFromTC();
1017 template <class Impl>
1019 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width)
1021 int idx = reg_idx + TheISA::FP_Base_DepTag;
1024 panic("Unimplemented!");
1027 thread->renameTable[idx]->setDoubleResult(val);
1030 panic("Unsupported width!");
1033 if (!thread->inSyscall) {
1034 cpu->squashFromTC();
1038 template <class Impl>
1040 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
1042 int idx = reg_idx + TheISA::FP_Base_DepTag;
1044 thread->renameTable[idx]->setDoubleResult(val);
1046 if (!thread->inSyscall) {
1047 cpu->squashFromTC();
1051 template <class Impl>
1053 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val,
1056 panic("Unimplemented!");
1059 template <class Impl>
1061 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
1063 panic("Unimplemented!");
1066 template <class Impl>
1068 OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
1071 cpu->frontEnd->setPC(val);
1073 if (!thread->inSyscall) {
1074 cpu->squashFromTC();
1078 template <class Impl>
1080 OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
1082 thread->nextPC = val;
1083 cpu->frontEnd->setNextPC(val);
1085 if (!thread->inSyscall) {
1086 cpu->squashFromTC();
1090 template <class Impl>
1092 OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
1094 return thread->miscRegFile.readReg(misc_reg);
1097 template <class Impl>
1099 OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg)
1101 return thread->miscRegFile.readRegWithEffect(misc_reg, this);
1104 template <class Impl>
1106 OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
1108 // Needs to setup a squash event unless we're in syscall mode
1109 thread->miscRegFile.setReg(misc_reg, val);
1111 if (!thread->inSyscall) {
1112 cpu->squashFromTC();
1116 template <class Impl>
1118 OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
1120 // Needs to setup a squash event unless we're in syscall mode
1121 thread->miscRegFile.setRegWithEffect(misc_reg, val, this);
1123 if (!thread->inSyscall) {
1124 cpu->squashFromTC();