2 * Copyright (c) 2006 The Regents of The University of Michigan
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32 #include "config/full_system.hh"
33 #include "config/use_checker.hh"
35 #include "arch/isa_traits.hh" // For MachInst
36 #include "base/trace.hh"
37 #include "cpu/base.hh"
38 #include "cpu/simple_thread.hh"
39 #include "cpu/thread_context.hh"
40 #include "cpu/exetrace.hh"
41 #include "cpu/ozone/cpu.hh"
42 #include "cpu/quiesce_event.hh"
43 #include "cpu/static_inst.hh"
44 #include "sim/sim_object.hh"
45 #include "sim/stats.hh"
48 #include "arch/faults.hh"
49 #include "arch/alpha/osfpal.hh"
50 #include "arch/tlb.hh"
51 #include "arch/types.hh"
52 #include "arch/kernel_stats.hh"
53 #include "arch/vtophys.hh"
54 #include "base/callback.hh"
55 #include "cpu/profile.hh"
56 #include "sim/faults.hh"
57 #include "sim/sim_events.hh"
58 #include "sim/sim_exit.hh"
59 #include "sim/system.hh"
61 #include "sim/process.hh"
65 #include "cpu/checker/thread_context.hh"
68 using namespace TheISA;
71 OzoneCPU<Impl>::TickEvent::TickEvent(OzoneCPU *c, int w)
72 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
78 OzoneCPU<Impl>::TickEvent::process()
85 OzoneCPU<Impl>::TickEvent::description()
87 return "OzoneCPU tick";
91 OzoneCPU<Impl>::OzoneCPU(Params *p)
93 : BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
95 : BaseCPU(p), thread(this, 0, p->workload[0], 0),
96 tickEvent(this, p->width),
100 frontEnd = new FrontEnd(p);
101 backEnd = new BackEnd(p);
107 BaseCPU *temp_checker = p->checker;
108 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
110 checker->setSystem(p->system);
112 checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
113 thread.tc = checkerTC;
116 panic("Checker enabled but not compiled in!");
119 // If checker is not being used, then the xcProxy points
120 // directly to the CPU's ExecContext.
122 thread.tc = &ozoneTC;
127 ozoneTC.thread = &thread;
129 thread.inSyscall = false;
131 thread.setStatus(ThreadContext::Suspended);
133 // Setup thread state stuff.
137 thread.quiesceEvent = new EndQuiesceEvent(tc);
142 physmem = p->system->physmem;
145 thread.profile = new FunctionProfile(p->system->kernelSymtab);
146 // @todo: This might be better as an ThreadContext instead of OzoneTC
148 new MakeCallback<OzoneTC,
149 &OzoneTC::dumpFuncProfile>(&ozoneTC);
150 registerExitCallback(cb);
153 // let's fill with a dummy node for now so we don't get a segfault
154 // on the first cycle when there's no node available.
155 static ProfileNode dummyNode;
156 thread.profileNode = &dummyNode;
157 thread.profilePC = 3;
160 #endif // !FULL_SYSTEM
165 threadContexts.push_back(tc);
167 frontEnd->setCPU(this);
168 backEnd->setCPU(this);
173 frontEnd->setThreadState(&thread);
174 backEnd->setThreadState(&thread);
176 frontEnd->setCommBuffer(&comm);
177 backEnd->setCommBuffer(&comm);
179 frontEnd->setBackEnd(backEnd);
180 backEnd->setFrontEnd(frontEnd);
186 // Setup rename table, initializing all values to ready.
187 for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
188 thread.renameTable[i] = new DynInst(this);
189 thread.renameTable[i]->setResultReady();
192 frontEnd->renameTable.copyFrom(thread.renameTable);
193 backEnd->renameTable.copyFrom(thread.renameTable);
197 FunctionalPort *phys_port;
198 VirtualPort *virt_port;
199 phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
201 mem_port = system->physmem->getPort("functional");
202 mem_port->setPeer(phys_port);
203 phys_port->setPeer(mem_port);
205 virt_port = new VirtualPort(csprintf("%s-%d-vport",
207 mem_port = system->physmem->getPort("functional");
208 mem_port->setPeer(virt_port);
209 virt_port->setPeer(mem_port);
211 thread.setPhysPort(phys_port);
212 thread.setVirtPort(virt_port);
215 DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
218 template <class Impl>
219 OzoneCPU<Impl>::~OzoneCPU()
223 template <class Impl>
225 OzoneCPU<Impl>::switchOut()
227 BaseCPU::switchOut();
229 // Front end needs state from back end, so switch out the back end first.
230 backEnd->switchOut();
231 frontEnd->switchOut();
234 template <class Impl>
236 OzoneCPU<Impl>::signalSwitched()
238 // Only complete the switchout when both the front end and back
239 // end have signalled they are ready to switch.
240 if (++switchCount == 2) {
241 backEnd->doSwitchOut();
242 frontEnd->doSwitchOut();
245 checker->switchOut();
248 _status = SwitchedOut;
250 // Loop through all registers
251 for (int i = 0; i < AlphaISA::TotalNumRegs; ++i) {
252 assert(thread.renameTable[i] == frontEnd->renameTable[i]);
254 assert(thread.renameTable[i] == backEnd->renameTable[i]);
256 DPRINTF(OzoneCPU, "Checking if register %i matches.\n", i);
260 if (tickEvent.scheduled())
263 assert(switchCount <= 2);
266 template <class Impl>
268 OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
270 BaseCPU::takeOverFrom(oldCPU);
272 thread.trapPending = false;
273 thread.inSyscall = false;
275 backEnd->takeOverFrom();
276 frontEnd->takeOverFrom();
277 frontEnd->renameTable.copyFrom(thread.renameTable);
278 backEnd->renameTable.copyFrom(thread.renameTable);
279 assert(!tickEvent.scheduled());
282 // Check rename table.
283 for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
284 assert(thread.renameTable[i]->isResultReady());
288 // @todo: Fix hardcoded number
289 // Clear out any old information in time buffer.
290 for (int i = 0; i < 15; ++i) {
294 // if any of this CPU's ThreadContexts are active, mark the CPU as
295 // running and schedule its tick event.
296 for (int i = 0; i < threadContexts.size(); ++i) {
297 ThreadContext *tc = threadContexts[i];
298 if (tc->status() == ThreadContext::Active &&
299 _status != Running) {
301 tickEvent.schedule(curTick);
304 // Nothing running, change status to reflect that we're no longer
306 if (_status == SwitchedOut) {
311 template <class Impl>
313 OzoneCPU<Impl>::activateContext(int thread_num, int delay)
315 // Eventually change this in SMT.
316 assert(thread_num == 0);
318 assert(_status == Idle);
320 scheduleTickEvent(delay);
323 if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
324 thread.quiesceEvent->deschedule();
326 thread.setStatus(ThreadContext::Active);
327 frontEnd->wakeFromQuiesce();
330 template <class Impl>
332 OzoneCPU<Impl>::suspendContext(int thread_num)
334 // Eventually change this in SMT.
335 assert(thread_num == 0);
336 // @todo: Figure out how to initially set the status properly so
338 // assert(_status == Running);
340 unscheduleTickEvent();
344 template <class Impl>
346 OzoneCPU<Impl>::deallocateContext(int thread_num, int delay)
348 // for now, these are equivalent
349 suspendContext(thread_num);
352 template <class Impl>
354 OzoneCPU<Impl>::haltContext(int thread_num)
356 // for now, these are equivalent
357 suspendContext(thread_num);
360 template <class Impl>
362 OzoneCPU<Impl>::regStats()
364 using namespace Stats;
369 .name(name() + ".num_insts")
370 .desc("Number of instructions executed")
374 .name(name() + ".num_refs")
375 .desc("Number of memory references")
379 .name(name() + ".not_idle_fraction")
380 .desc("Percentage of non-idle cycles")
384 .name(name() + ".idle_fraction")
385 .desc("Percentage of idle cycles")
389 .name(name() + ".quiesce_cycles")
390 .desc("Number of cycles spent in quiesce")
393 idleFraction = constant(1.0) - notIdleFraction;
395 frontEnd->regStats();
399 template <class Impl>
401 OzoneCPU<Impl>::resetStats()
403 // startNumInst = numInst;
404 notIdleFraction = (_status != Idle);
407 template <class Impl>
409 OzoneCPU<Impl>::init()
413 // Mark this as in syscall so it won't need to squash
414 thread.inSyscall = true;
416 for (int i = 0; i < threadContexts.size(); ++i) {
417 ThreadContext *tc = threadContexts[i];
419 // initialize CPU, including PC
420 TheISA::initCPU(tc, tc->readCpuId());
423 frontEnd->renameTable.copyFrom(thread.renameTable);
424 backEnd->renameTable.copyFrom(thread.renameTable);
426 thread.inSyscall = false;
429 template <class Impl>
431 OzoneCPU<Impl>::getPort(const std::string &if_name, int idx)
433 if (if_name == "dcache_port")
434 return backEnd->getDcachePort();
435 else if (if_name == "icache_port")
436 return frontEnd->getIcachePort();
438 panic("No Such Port\n");
441 template <class Impl>
443 OzoneCPU<Impl>::serialize(std::ostream &os)
445 BaseCPU::serialize(os);
446 SERIALIZE_ENUM(_status);
447 nameOut(os, csprintf("%s.tc", name()));
448 ozoneTC.serialize(os);
449 nameOut(os, csprintf("%s.tickEvent", name()));
450 tickEvent.serialize(os);
452 // Use SimpleThread's ability to checkpoint to make it easier to
453 // write out the registers. Also make this static so it doesn't
454 // get instantiated multiple times (causes a panic in statistics).
455 static SimpleThread temp;
457 nameOut(os, csprintf("%s.xc.0", name()));
458 temp.copyTC(thread.getTC());
462 template <class Impl>
464 OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
466 BaseCPU::unserialize(cp, section);
467 UNSERIALIZE_ENUM(_status);
468 ozoneTC.unserialize(cp, csprintf("%s.tc", section));
469 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
471 // Use SimpleThread's ability to checkpoint to make it easier to
472 // read in the registers. Also make this static so it doesn't
473 // get instantiated multiple times (causes a panic in statistics).
474 static SimpleThread temp;
476 temp.copyTC(thread.getTC());
477 temp.unserialize(cp, csprintf("%s.xc.0", section));
478 thread.getTC()->copyArchRegs(temp.getTC());
481 template <class Impl>
483 OzoneCPU<Impl>::copySrcTranslate(Addr src)
485 panic("Copy not implemented!\n");
488 static bool no_warn = true;
489 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
490 // Only support block sizes of 64 atm.
491 assert(blk_size == 64);
492 int offset = src & (blk_size - 1);
494 // Make sure block doesn't span page
496 (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
497 (src >> 40) != 0xfffffc) {
498 warn("Copied block source spans pages %x.", src);
502 memReq->reset(src & ~(blk_size - 1), blk_size);
504 // translate to physical address
505 Fault fault = tc->translateDataReadReq(memReq);
507 assert(fault != Alignment_Fault);
509 if (fault == NoFault) {
510 tc->copySrcAddr = src;
511 tc->copySrcPhysAddr = memReq->paddr + offset;
514 tc->copySrcPhysAddr = 0;
520 template <class Impl>
522 OzoneCPU<Impl>::copy(Addr dest)
524 panic("Copy not implemented!\n");
527 static bool no_warn = true;
528 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
529 // Only support block sizes of 64 atm.
530 assert(blk_size == 64);
531 uint8_t data[blk_size];
532 //assert(tc->copySrcAddr);
533 int offset = dest & (blk_size - 1);
535 // Make sure block doesn't span page
537 (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
538 (dest >> 40) != 0xfffffc) {
540 warn("Copied block destination spans pages %x. ", dest);
543 memReq->reset(dest & ~(blk_size -1), blk_size);
544 // translate to physical address
545 Fault fault = tc->translateDataWriteReq(memReq);
547 assert(fault != Alignment_Fault);
549 if (fault == NoFault) {
550 Addr dest_addr = memReq->paddr + offset;
551 // Need to read straight from memory since we have more than 8 bytes.
552 memReq->paddr = tc->copySrcPhysAddr;
553 tc->mem->read(memReq, data);
554 memReq->paddr = dest_addr;
555 tc->mem->write(memReq, data);
556 if (dcacheInterface) {
558 memReq->completionEvent = NULL;
559 memReq->paddr = tc->copySrcPhysAddr;
560 memReq->dest = dest_addr;
562 memReq->time = curTick;
563 dcacheInterface->access(memReq);
571 template <class Impl>
573 OzoneCPU<Impl>::dbg_vtophys(Addr addr)
575 return vtophys(tc, addr);
577 #endif // FULL_SYSTEM
580 template <class Impl>
582 OzoneCPU<Impl>::post_interrupt(int int_num, int index)
584 BaseCPU::post_interrupt(int_num, index);
586 if (_status == Idle) {
587 DPRINTF(IPI,"Suspended Processor awoke\n");
588 // thread.activate();
589 // Hack for now. Otherwise might have to go through the tc, or
590 // I need to figure out what's the right thing to call.
591 activateContext(thread.readTid(), 1);
594 #endif // FULL_SYSTEM
596 /* start simulation, program loaded, processor precise state initialized */
597 template <class Impl>
599 OzoneCPU<Impl>::tick()
601 DPRINTF(OzoneCPU, "\n\nOzoneCPU: Ticking cpu.\n");
604 thread.renameTable[ZeroReg]->setIntResult(0);
605 thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
606 setDoubleResult(0.0);
612 // check for instruction-count-based events
613 comInstEventQueue[0]->serviceEvents(numInst);
615 if (!tickEvent.scheduled() && _status == Running)
616 tickEvent.schedule(curTick + cycles(1));
619 template <class Impl>
621 OzoneCPU<Impl>::squashFromTC()
623 thread.inSyscall = true;
624 backEnd->generateTCEvent();
628 template <class Impl>
630 OzoneCPU<Impl>::syscall(uint64_t &callnum)
632 // Not sure this copy is needed, depending on how the TC proxy is made.
633 thread.renameTable.copyFrom(backEnd->renameTable);
635 thread.inSyscall = true;
637 thread.funcExeInst++;
639 DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst);
641 thread.process->syscall(callnum, tc);
643 thread.funcExeInst--;
645 thread.inSyscall = false;
647 frontEnd->renameTable.copyFrom(thread.renameTable);
648 backEnd->renameTable.copyFrom(thread.renameTable);
651 template <class Impl>
653 OzoneCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
655 // check for error condition. Alpha syscall convention is to
656 // indicate success/failure in reg a3 (r19) and put the
657 // return value itself in the standard return value reg (v0).
658 if (return_value.successful()) {
660 thread.renameTable[SyscallSuccessReg]->setIntResult(0);
661 thread.renameTable[ReturnValueReg]->setIntResult(
662 return_value.value());
664 // got an error, return details
665 thread.renameTable[SyscallSuccessReg]->setIntResult((IntReg) -1);
666 thread.renameTable[ReturnValueReg]->setIntResult(
667 -return_value.value());
671 template <class Impl>
673 OzoneCPU<Impl>::hwrei()
675 // Need to move this to ISA code
676 // May also need to make this per thread
679 lockAddrList.clear();
680 thread.kernelStats->hwrei();
682 // FIXME: XXX check for interrupts? XXX
686 template <class Impl>
688 OzoneCPU<Impl>::processInterrupts()
690 // Check for interrupts here. For now can copy the code that
691 // exists within isa_fullsys_traits.hh. Also assume that thread 0
692 // is the one that handles the interrupts.
694 // Check if there are any outstanding interrupts
695 //Handle the interrupts
696 Fault interrupt = this->interrupts.getInterrupt(thread.getTC());
698 if (interrupt != NoFault) {
699 this->interrupts.updateIntrInfo(thread.getTC());
700 interrupt->invoke(thread.getTC());
704 template <class Impl>
706 OzoneCPU<Impl>::simPalCheck(int palFunc)
708 // Need to move this to ISA code
709 // May also need to make this per thread
710 thread.kernelStats->callpal(palFunc, tc);
714 haltContext(thread.readTid());
715 if (--System::numSystemsRunning == 0)
716 exitSimLoop("all cpus halted");
721 if (system->breakpoint())
730 template <class Impl>
732 OzoneCPU<Impl>::OzoneTC::getCpuPtr()
737 template <class Impl>
739 OzoneCPU<Impl>::OzoneTC::setCpuId(int id)
742 thread->setCpuId(id);
746 template <class Impl>
748 OzoneCPU<Impl>::OzoneTC::delVirtPort(VirtualPort *vp)
755 template <class Impl>
757 OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
759 thread->setStatus(new_status);
762 template <class Impl>
764 OzoneCPU<Impl>::OzoneTC::activate(int delay)
766 cpu->activateContext(thread->readTid(), delay);
769 /// Set the status to Suspended.
770 template <class Impl>
772 OzoneCPU<Impl>::OzoneTC::suspend()
774 cpu->suspendContext(thread->readTid());
777 /// Set the status to Unallocated.
778 template <class Impl>
780 OzoneCPU<Impl>::OzoneTC::deallocate(int delay)
782 cpu->deallocateContext(thread->readTid(), delay);
785 /// Set the status to Halted.
786 template <class Impl>
788 OzoneCPU<Impl>::OzoneTC::halt()
790 cpu->haltContext(thread->readTid());
794 template <class Impl>
796 OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
798 thread->dumpFuncProfile();
802 template <class Impl>
804 OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
806 // some things should already be set up
808 assert(getSystemPtr() == old_context->getSystemPtr());
810 assert(getProcessPtr() == old_context->getProcessPtr());
813 // copy over functional state
814 setStatus(old_context->status());
815 copyArchRegs(old_context);
816 setCpuId(old_context->readCpuId());
818 thread->setInst(old_context->getInst());
820 setFuncExeInst(old_context->readFuncExeInst());
822 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
824 // Point the quiesce event's TC at this TC so that it wakes up
826 other_quiesce->tc = this;
828 if (thread->quiesceEvent) {
829 thread->quiesceEvent->tc = this;
832 // Copy kernel stats pointer from old context.
833 thread->kernelStats = old_context->getKernelStats();
834 // storeCondFailures = 0;
835 cpu->lockFlag = false;
838 old_context->setStatus(ThreadContext::Unallocated);
841 template <class Impl>
843 OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
846 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
847 thread->kernelStats->regStats(name + ".kern");
851 template <class Impl>
853 OzoneCPU<Impl>::OzoneTC::serialize(std::ostream &os)
855 // Once serialization is added, serialize the quiesce event and
856 // kernel stats. Will need to make sure there aren't multiple
857 // things that serialize them.
860 template <class Impl>
862 OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string §ion)
866 template <class Impl>
868 OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
870 return thread->quiesceEvent;
873 template <class Impl>
875 OzoneCPU<Impl>::OzoneTC::readLastActivate()
877 return thread->lastActivate;
880 template <class Impl>
882 OzoneCPU<Impl>::OzoneTC::readLastSuspend()
884 return thread->lastSuspend;
887 template <class Impl>
889 OzoneCPU<Impl>::OzoneTC::profileClear()
891 thread->profileClear();
894 template <class Impl>
896 OzoneCPU<Impl>::OzoneTC::profileSample()
898 thread->profileSample();
902 template <class Impl>
904 OzoneCPU<Impl>::OzoneTC::getThreadNum()
906 return thread->readTid();
909 template <class Impl>
911 OzoneCPU<Impl>::OzoneTC::getInst()
913 return thread->getInst();
916 template <class Impl>
918 OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
920 thread->PC = tc->readPC();
921 thread->nextPC = tc->readNextPC();
923 cpu->frontEnd->setPC(thread->PC);
924 cpu->frontEnd->setNextPC(thread->nextPC);
926 // First loop through the integer registers.
927 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
928 /* DPRINTF(OzoneCPU, "Copying over register %i, had data %lli, "
929 "now has data %lli.\n",
930 i, thread->renameTable[i]->readIntResult(),
933 thread->renameTable[i]->setIntResult(tc->readIntReg(i));
936 // Then loop through the floating point registers.
937 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
938 int fp_idx = i + TheISA::FP_Base_DepTag;
939 thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
943 thread->funcExeInst = tc->readFuncExeInst();
946 // Need to copy the TC values into the current rename table,
947 // copy the misc regs.
948 copyMiscRegs(tc, this);
951 template <class Impl>
953 OzoneCPU<Impl>::OzoneTC::clearArchRegs()
955 panic("Unimplemented!");
958 template <class Impl>
960 OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx)
962 return thread->renameTable[reg_idx]->readIntResult();
965 template <class Impl>
967 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width)
969 int idx = reg_idx + TheISA::FP_Base_DepTag;
972 return thread->renameTable[idx]->readFloatResult();
974 return thread->renameTable[idx]->readDoubleResult();
976 panic("Unsupported width!");
981 template <class Impl>
983 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
985 int idx = reg_idx + TheISA::FP_Base_DepTag;
986 return thread->renameTable[idx]->readFloatResult();
989 template <class Impl>
991 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width)
993 int idx = reg_idx + TheISA::FP_Base_DepTag;
994 return thread->renameTable[idx]->readIntResult();
997 template <class Impl>
999 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
1001 int idx = reg_idx + TheISA::FP_Base_DepTag;
1002 return thread->renameTable[idx]->readIntResult();
1005 template <class Impl>
1007 OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
1009 thread->renameTable[reg_idx]->setIntResult(val);
1011 if (!thread->inSyscall) {
1012 cpu->squashFromTC();
1016 template <class Impl>
1018 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width)
1020 int idx = reg_idx + TheISA::FP_Base_DepTag;
1023 panic("Unimplemented!");
1026 thread->renameTable[idx]->setDoubleResult(val);
1029 panic("Unsupported width!");
1032 if (!thread->inSyscall) {
1033 cpu->squashFromTC();
1037 template <class Impl>
1039 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
1041 int idx = reg_idx + TheISA::FP_Base_DepTag;
1043 thread->renameTable[idx]->setDoubleResult(val);
1045 if (!thread->inSyscall) {
1046 cpu->squashFromTC();
1050 template <class Impl>
1052 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val,
1055 panic("Unimplemented!");
1058 template <class Impl>
1060 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
1062 panic("Unimplemented!");
1065 template <class Impl>
1067 OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
1070 cpu->frontEnd->setPC(val);
1072 if (!thread->inSyscall) {
1073 cpu->squashFromTC();
1077 template <class Impl>
1079 OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
1081 thread->nextPC = val;
1082 cpu->frontEnd->setNextPC(val);
1084 if (!thread->inSyscall) {
1085 cpu->squashFromTC();
1089 template <class Impl>
1091 OzoneCPU<Impl>::OzoneTC::readMiscRegNoEffect(int misc_reg)
1093 return thread->miscRegFile.readRegNoEffect(misc_reg);
1096 template <class Impl>
1098 OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
1100 return thread->miscRegFile.readReg(misc_reg, this);
1103 template <class Impl>
1105 OzoneCPU<Impl>::OzoneTC::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
1107 // Needs to setup a squash event unless we're in syscall mode
1108 thread->miscRegFile.setRegNoEffect(misc_reg, val);
1110 if (!thread->inSyscall) {
1111 cpu->squashFromTC();
1115 template <class Impl>
1117 OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
1119 // Needs to setup a squash event unless we're in syscall mode
1120 thread->miscRegFile.setReg(misc_reg, val, this);
1122 if (!thread->inSyscall) {
1123 cpu->squashFromTC();