2 * Copyright (c) 2006 The Regents of The University of Michigan
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32 #include "config/full_system.hh"
33 #include "config/use_checker.hh"
35 #include "arch/isa_traits.hh" // For MachInst
36 #include "base/trace.hh"
37 #include "cpu/base.hh"
38 #include "cpu/simple_thread.hh"
39 #include "cpu/thread_context.hh"
40 #include "cpu/exetrace.hh"
41 #include "cpu/ozone/cpu.hh"
42 #include "cpu/quiesce_event.hh"
43 #include "cpu/static_inst.hh"
44 #include "sim/sim_object.hh"
45 #include "sim/stats.hh"
48 #include "arch/faults.hh"
49 #include "arch/alpha/osfpal.hh"
50 #include "arch/alpha/tlb.hh"
51 #include "arch/alpha/types.hh"
52 #include "arch/vtophys.hh"
53 #include "base/callback.hh"
54 #include "cpu/profile.hh"
55 #include "kern/kernel_stats.hh"
56 #include "mem/physical.hh"
57 #include "sim/faults.hh"
58 #include "sim/sim_events.hh"
59 #include "sim/sim_exit.hh"
60 #include "sim/system.hh"
62 #include "sim/process.hh"
66 #include "cpu/checker/thread_context.hh"
69 using namespace TheISA;
72 OzoneCPU<Impl>::TickEvent::TickEvent(OzoneCPU *c, int w)
73 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
79 OzoneCPU<Impl>::TickEvent::process()
86 OzoneCPU<Impl>::TickEvent::description()
88 return "OzoneCPU tick event";
92 OzoneCPU<Impl>::OzoneCPU(Params *p)
94 : BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
96 : BaseCPU(p), thread(this, 0, p->workload[0], 0),
97 tickEvent(this, p->width),
101 frontEnd = new FrontEnd(p);
102 backEnd = new BackEnd(p);
108 BaseCPU *temp_checker = p->checker;
109 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
111 checker->setSystem(p->system);
113 checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
114 thread.tc = checkerTC;
117 panic("Checker enabled but not compiled in!");
120 // If checker is not being used, then the xcProxy points
121 // directly to the CPU's ExecContext.
123 thread.tc = &ozoneTC;
128 ozoneTC.thread = &thread;
130 thread.inSyscall = false;
132 thread.setStatus(ThreadContext::Suspended);
134 // Setup thread state stuff.
138 thread.quiesceEvent = new EndQuiesceEvent(tc);
143 physmem = p->system->physmem;
146 thread.profile = new FunctionProfile(p->system->kernelSymtab);
147 // @todo: This might be better as an ThreadContext instead of OzoneTC
149 new MakeCallback<OzoneTC,
150 &OzoneTC::dumpFuncProfile>(&ozoneTC);
151 registerExitCallback(cb);
154 // let's fill with a dummy node for now so we don't get a segfault
155 // on the first cycle when there's no node available.
156 static ProfileNode dummyNode;
157 thread.profileNode = &dummyNode;
158 thread.profilePC = 3;
161 #endif // !FULL_SYSTEM
166 threadContexts.push_back(tc);
168 frontEnd->setCPU(this);
169 backEnd->setCPU(this);
174 frontEnd->setThreadState(&thread);
175 backEnd->setThreadState(&thread);
177 frontEnd->setCommBuffer(&comm);
178 backEnd->setCommBuffer(&comm);
180 frontEnd->setBackEnd(backEnd);
181 backEnd->setFrontEnd(frontEnd);
186 checkInterrupts = false;
191 // Setup rename table, initializing all values to ready.
192 for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
193 thread.renameTable[i] = new DynInst(this);
194 thread.renameTable[i]->setResultReady();
197 frontEnd->renameTable.copyFrom(thread.renameTable);
198 backEnd->renameTable.copyFrom(thread.renameTable);
202 FunctionalPort *phys_port;
203 VirtualPort *virt_port;
204 phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
206 mem_port = system->physmem->getPort("functional");
207 mem_port->setPeer(phys_port);
208 phys_port->setPeer(mem_port);
210 virt_port = new VirtualPort(csprintf("%s-%d-vport",
212 mem_port = system->physmem->getPort("functional");
213 mem_port->setPeer(virt_port);
214 virt_port->setPeer(mem_port);
216 thread.setPhysPort(phys_port);
217 thread.setVirtPort(virt_port);
220 DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
223 template <class Impl>
224 OzoneCPU<Impl>::~OzoneCPU()
228 template <class Impl>
230 OzoneCPU<Impl>::switchOut()
232 BaseCPU::switchOut();
234 // Front end needs state from back end, so switch out the back end first.
235 backEnd->switchOut();
236 frontEnd->switchOut();
239 template <class Impl>
241 OzoneCPU<Impl>::signalSwitched()
243 // Only complete the switchout when both the front end and back
244 // end have signalled they are ready to switch.
245 if (++switchCount == 2) {
246 backEnd->doSwitchOut();
247 frontEnd->doSwitchOut();
250 checker->switchOut();
253 _status = SwitchedOut;
255 // Loop through all registers
256 for (int i = 0; i < AlphaISA::TotalNumRegs; ++i) {
257 assert(thread.renameTable[i] == frontEnd->renameTable[i]);
259 assert(thread.renameTable[i] == backEnd->renameTable[i]);
261 DPRINTF(OzoneCPU, "Checking if register %i matches.\n", i);
265 if (tickEvent.scheduled())
268 assert(switchCount <= 2);
271 template <class Impl>
273 OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
275 BaseCPU::takeOverFrom(oldCPU);
277 thread.trapPending = false;
278 thread.inSyscall = false;
280 backEnd->takeOverFrom();
281 frontEnd->takeOverFrom();
282 frontEnd->renameTable.copyFrom(thread.renameTable);
283 backEnd->renameTable.copyFrom(thread.renameTable);
284 assert(!tickEvent.scheduled());
287 // Check rename table.
288 for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
289 assert(thread.renameTable[i]->isResultReady());
293 // @todo: Fix hardcoded number
294 // Clear out any old information in time buffer.
295 for (int i = 0; i < 15; ++i) {
299 // if any of this CPU's ThreadContexts are active, mark the CPU as
300 // running and schedule its tick event.
301 for (int i = 0; i < threadContexts.size(); ++i) {
302 ThreadContext *tc = threadContexts[i];
303 if (tc->status() == ThreadContext::Active &&
304 _status != Running) {
306 tickEvent.schedule(curTick);
309 // Nothing running, change status to reflect that we're no longer
311 if (_status == SwitchedOut) {
316 template <class Impl>
318 OzoneCPU<Impl>::activateContext(int thread_num, int delay)
320 // Eventually change this in SMT.
321 assert(thread_num == 0);
323 assert(_status == Idle);
325 scheduleTickEvent(delay);
328 if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
329 thread.quiesceEvent->deschedule();
331 thread.setStatus(ThreadContext::Active);
332 frontEnd->wakeFromQuiesce();
335 template <class Impl>
337 OzoneCPU<Impl>::suspendContext(int thread_num)
339 // Eventually change this in SMT.
340 assert(thread_num == 0);
341 // @todo: Figure out how to initially set the status properly so
343 // assert(_status == Running);
345 unscheduleTickEvent();
349 template <class Impl>
351 OzoneCPU<Impl>::deallocateContext(int thread_num, int delay)
353 // for now, these are equivalent
354 suspendContext(thread_num);
357 template <class Impl>
359 OzoneCPU<Impl>::haltContext(int thread_num)
361 // for now, these are equivalent
362 suspendContext(thread_num);
365 template <class Impl>
367 OzoneCPU<Impl>::regStats()
369 using namespace Stats;
374 .name(name() + ".num_insts")
375 .desc("Number of instructions executed")
379 .name(name() + ".num_refs")
380 .desc("Number of memory references")
384 .name(name() + ".not_idle_fraction")
385 .desc("Percentage of non-idle cycles")
389 .name(name() + ".idle_fraction")
390 .desc("Percentage of idle cycles")
394 .name(name() + ".quiesce_cycles")
395 .desc("Number of cycles spent in quiesce")
398 idleFraction = constant(1.0) - notIdleFraction;
400 frontEnd->regStats();
404 template <class Impl>
406 OzoneCPU<Impl>::resetStats()
408 // startNumInst = numInst;
409 notIdleFraction = (_status != Idle);
412 template <class Impl>
414 OzoneCPU<Impl>::init()
418 // Mark this as in syscall so it won't need to squash
419 thread.inSyscall = true;
421 for (int i = 0; i < threadContexts.size(); ++i) {
422 ThreadContext *tc = threadContexts[i];
424 // initialize CPU, including PC
425 TheISA::initCPU(tc, tc->readCpuId());
428 frontEnd->renameTable.copyFrom(thread.renameTable);
429 backEnd->renameTable.copyFrom(thread.renameTable);
431 thread.inSyscall = false;
434 template <class Impl>
436 OzoneCPU<Impl>::getPort(const std::string &if_name, int idx)
438 if (if_name == "dcache_port")
439 return backEnd->getDcachePort();
440 else if (if_name == "icache_port")
441 return frontEnd->getIcachePort();
443 panic("No Such Port\n");
446 template <class Impl>
448 OzoneCPU<Impl>::serialize(std::ostream &os)
450 BaseCPU::serialize(os);
451 SERIALIZE_ENUM(_status);
452 nameOut(os, csprintf("%s.tc", name()));
453 ozoneTC.serialize(os);
454 nameOut(os, csprintf("%s.tickEvent", name()));
455 tickEvent.serialize(os);
457 // Use SimpleThread's ability to checkpoint to make it easier to
458 // write out the registers. Also make this static so it doesn't
459 // get instantiated multiple times (causes a panic in statistics).
460 static SimpleThread temp;
462 nameOut(os, csprintf("%s.xc.0", name()));
463 temp.copyTC(thread.getTC());
467 template <class Impl>
469 OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
471 BaseCPU::unserialize(cp, section);
472 UNSERIALIZE_ENUM(_status);
473 ozoneTC.unserialize(cp, csprintf("%s.tc", section));
474 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
476 // Use SimpleThread's ability to checkpoint to make it easier to
477 // read in the registers. Also make this static so it doesn't
478 // get instantiated multiple times (causes a panic in statistics).
479 static SimpleThread temp;
481 temp.copyTC(thread.getTC());
482 temp.unserialize(cp, csprintf("%s.xc.0", section));
483 thread.getTC()->copyArchRegs(temp.getTC());
486 template <class Impl>
488 OzoneCPU<Impl>::copySrcTranslate(Addr src)
490 panic("Copy not implemented!\n");
493 static bool no_warn = true;
494 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
495 // Only support block sizes of 64 atm.
496 assert(blk_size == 64);
497 int offset = src & (blk_size - 1);
499 // Make sure block doesn't span page
501 (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
502 (src >> 40) != 0xfffffc) {
503 warn("Copied block source spans pages %x.", src);
507 memReq->reset(src & ~(blk_size - 1), blk_size);
509 // translate to physical address
510 Fault fault = tc->translateDataReadReq(memReq);
512 assert(fault != Alignment_Fault);
514 if (fault == NoFault) {
515 tc->copySrcAddr = src;
516 tc->copySrcPhysAddr = memReq->paddr + offset;
519 tc->copySrcPhysAddr = 0;
525 template <class Impl>
527 OzoneCPU<Impl>::copy(Addr dest)
529 panic("Copy not implemented!\n");
532 static bool no_warn = true;
533 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
534 // Only support block sizes of 64 atm.
535 assert(blk_size == 64);
536 uint8_t data[blk_size];
537 //assert(tc->copySrcAddr);
538 int offset = dest & (blk_size - 1);
540 // Make sure block doesn't span page
542 (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
543 (dest >> 40) != 0xfffffc) {
545 warn("Copied block destination spans pages %x. ", dest);
548 memReq->reset(dest & ~(blk_size -1), blk_size);
549 // translate to physical address
550 Fault fault = tc->translateDataWriteReq(memReq);
552 assert(fault != Alignment_Fault);
554 if (fault == NoFault) {
555 Addr dest_addr = memReq->paddr + offset;
556 // Need to read straight from memory since we have more than 8 bytes.
557 memReq->paddr = tc->copySrcPhysAddr;
558 tc->mem->read(memReq, data);
559 memReq->paddr = dest_addr;
560 tc->mem->write(memReq, data);
561 if (dcacheInterface) {
563 memReq->completionEvent = NULL;
564 memReq->paddr = tc->copySrcPhysAddr;
565 memReq->dest = dest_addr;
567 memReq->time = curTick;
568 dcacheInterface->access(memReq);
576 template <class Impl>
578 OzoneCPU<Impl>::dbg_vtophys(Addr addr)
580 return vtophys(tc, addr);
582 #endif // FULL_SYSTEM
585 template <class Impl>
587 OzoneCPU<Impl>::post_interrupt(int int_num, int index)
589 BaseCPU::post_interrupt(int_num, index);
591 if (_status == Idle) {
592 DPRINTF(IPI,"Suspended Processor awoke\n");
593 // thread.activate();
594 // Hack for now. Otherwise might have to go through the tc, or
595 // I need to figure out what's the right thing to call.
596 activateContext(thread.readTid(), 1);
599 #endif // FULL_SYSTEM
601 /* start simulation, program loaded, processor precise state initialized */
602 template <class Impl>
604 OzoneCPU<Impl>::tick()
606 DPRINTF(OzoneCPU, "\n\nOzoneCPU: Ticking cpu.\n");
609 thread.renameTable[ZeroReg]->setIntResult(0);
610 thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
611 setDoubleResult(0.0);
617 // check for instruction-count-based events
618 comInstEventQueue[0]->serviceEvents(numInst);
620 if (!tickEvent.scheduled() && _status == Running)
621 tickEvent.schedule(curTick + cycles(1));
624 template <class Impl>
626 OzoneCPU<Impl>::squashFromTC()
628 thread.inSyscall = true;
629 backEnd->generateTCEvent();
633 template <class Impl>
635 OzoneCPU<Impl>::syscall(uint64_t &callnum)
637 // Not sure this copy is needed, depending on how the TC proxy is made.
638 thread.renameTable.copyFrom(backEnd->renameTable);
640 thread.inSyscall = true;
642 thread.funcExeInst++;
644 DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst);
646 thread.process->syscall(callnum, tc);
648 thread.funcExeInst--;
650 thread.inSyscall = false;
652 frontEnd->renameTable.copyFrom(thread.renameTable);
653 backEnd->renameTable.copyFrom(thread.renameTable);
656 template <class Impl>
658 OzoneCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
660 // check for error condition. Alpha syscall convention is to
661 // indicate success/failure in reg a3 (r19) and put the
662 // return value itself in the standard return value reg (v0).
663 if (return_value.successful()) {
665 thread.renameTable[SyscallSuccessReg]->setIntResult(0);
666 thread.renameTable[ReturnValueReg]->setIntResult(
667 return_value.value());
669 // got an error, return details
670 thread.renameTable[SyscallSuccessReg]->setIntResult((IntReg) -1);
671 thread.renameTable[ReturnValueReg]->setIntResult(
672 -return_value.value());
676 template <class Impl>
678 OzoneCPU<Impl>::hwrei()
680 // Need to move this to ISA code
681 // May also need to make this per thread
684 lockAddrList.clear();
685 thread.kernelStats->hwrei();
687 checkInterrupts = true;
689 // FIXME: XXX check for interrupts? XXX
693 template <class Impl>
695 OzoneCPU<Impl>::processInterrupts()
697 // Check for interrupts here. For now can copy the code that
698 // exists within isa_fullsys_traits.hh. Also assume that thread 0
699 // is the one that handles the interrupts.
701 // Check if there are any outstanding interrupts
702 //Handle the interrupts
706 checkInterrupts = false;
708 if (thread.readMiscReg(IPR_ASTRR))
709 panic("asynchronous traps not implemented\n");
711 if (thread.readMiscReg(IPR_SIRR)) {
712 for (int i = INTLEVEL_SOFTWARE_MIN;
713 i < INTLEVEL_SOFTWARE_MAX; i++) {
714 if (thread.readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
715 // See table 4-19 of the 21164 hardware reference
716 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
717 summary |= (ULL(1) << i);
722 uint64_t interrupts = intr_status();
725 for (int i = INTLEVEL_EXTERNAL_MIN;
726 i < INTLEVEL_EXTERNAL_MAX; i++) {
727 if (interrupts & (ULL(1) << i)) {
728 // See table 4-19 of the 21164 hardware reference
730 summary |= (ULL(1) << i);
735 if (ipl && ipl > thread.readMiscReg(IPR_IPLR)) {
736 thread.setMiscReg(IPR_ISR, summary);
737 thread.setMiscReg(IPR_INTID, ipl);
739 // @todo: Make this more transparent
741 checker->threadBase()->setMiscReg(IPR_ISR, summary);
742 checker->threadBase()->setMiscReg(IPR_INTID, ipl);
745 Fault fault = new InterruptFault;
746 fault->invoke(thread.getTC());
747 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
748 thread.readMiscReg(IPR_IPLR), ipl, summary);
752 template <class Impl>
754 OzoneCPU<Impl>::simPalCheck(int palFunc)
756 // Need to move this to ISA code
757 // May also need to make this per thread
758 thread.kernelStats->callpal(palFunc, tc);
762 haltContext(thread.readTid());
763 if (--System::numSystemsRunning == 0)
764 exitSimLoop("all cpus halted");
769 if (system->breakpoint())
778 template <class Impl>
780 OzoneCPU<Impl>::OzoneTC::getCpuPtr()
785 template <class Impl>
787 OzoneCPU<Impl>::OzoneTC::setCpuId(int id)
790 thread->setCpuId(id);
794 template <class Impl>
796 OzoneCPU<Impl>::OzoneTC::delVirtPort(VirtualPort *vp)
798 delete vp->getPeer();
803 template <class Impl>
805 OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
807 thread->setStatus(new_status);
810 template <class Impl>
812 OzoneCPU<Impl>::OzoneTC::activate(int delay)
814 cpu->activateContext(thread->readTid(), delay);
817 /// Set the status to Suspended.
818 template <class Impl>
820 OzoneCPU<Impl>::OzoneTC::suspend()
822 cpu->suspendContext(thread->readTid());
825 /// Set the status to Unallocated.
826 template <class Impl>
828 OzoneCPU<Impl>::OzoneTC::deallocate(int delay)
830 cpu->deallocateContext(thread->readTid(), delay);
833 /// Set the status to Halted.
834 template <class Impl>
836 OzoneCPU<Impl>::OzoneTC::halt()
838 cpu->haltContext(thread->readTid());
842 template <class Impl>
844 OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
846 thread->dumpFuncProfile();
850 template <class Impl>
852 OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
854 // some things should already be set up
856 assert(getSystemPtr() == old_context->getSystemPtr());
858 assert(getProcessPtr() == old_context->getProcessPtr());
861 // copy over functional state
862 setStatus(old_context->status());
863 copyArchRegs(old_context);
864 setCpuId(old_context->readCpuId());
866 thread->setInst(old_context->getInst());
868 setFuncExeInst(old_context->readFuncExeInst());
870 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
872 // Point the quiesce event's TC at this TC so that it wakes up
874 other_quiesce->tc = this;
876 if (thread->quiesceEvent) {
877 thread->quiesceEvent->tc = this;
880 // Copy kernel stats pointer from old context.
881 thread->kernelStats = old_context->getKernelStats();
882 // storeCondFailures = 0;
883 cpu->lockFlag = false;
886 old_context->setStatus(ThreadContext::Unallocated);
889 template <class Impl>
891 OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
894 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
895 thread->kernelStats->regStats(name + ".kern");
899 template <class Impl>
901 OzoneCPU<Impl>::OzoneTC::serialize(std::ostream &os)
903 // Once serialization is added, serialize the quiesce event and
904 // kernel stats. Will need to make sure there aren't multiple
905 // things that serialize them.
908 template <class Impl>
910 OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string §ion)
914 template <class Impl>
916 OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
918 return thread->quiesceEvent;
921 template <class Impl>
923 OzoneCPU<Impl>::OzoneTC::readLastActivate()
925 return thread->lastActivate;
928 template <class Impl>
930 OzoneCPU<Impl>::OzoneTC::readLastSuspend()
932 return thread->lastSuspend;
935 template <class Impl>
937 OzoneCPU<Impl>::OzoneTC::profileClear()
939 thread->profileClear();
942 template <class Impl>
944 OzoneCPU<Impl>::OzoneTC::profileSample()
946 thread->profileSample();
950 template <class Impl>
952 OzoneCPU<Impl>::OzoneTC::getThreadNum()
954 return thread->readTid();
957 template <class Impl>
959 OzoneCPU<Impl>::OzoneTC::getInst()
961 return thread->getInst();
964 template <class Impl>
966 OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
968 thread->PC = tc->readPC();
969 thread->nextPC = tc->readNextPC();
971 cpu->frontEnd->setPC(thread->PC);
972 cpu->frontEnd->setNextPC(thread->nextPC);
974 // First loop through the integer registers.
975 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
976 /* DPRINTF(OzoneCPU, "Copying over register %i, had data %lli, "
977 "now has data %lli.\n",
978 i, thread->renameTable[i]->readIntResult(),
981 thread->renameTable[i]->setIntResult(tc->readIntReg(i));
984 // Then loop through the floating point registers.
985 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
986 int fp_idx = i + TheISA::FP_Base_DepTag;
987 thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
991 thread->funcExeInst = tc->readFuncExeInst();
994 // Need to copy the TC values into the current rename table,
995 // copy the misc regs.
996 copyMiscRegs(tc, this);
999 template <class Impl>
1001 OzoneCPU<Impl>::OzoneTC::clearArchRegs()
1003 panic("Unimplemented!");
1006 template <class Impl>
1008 OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx)
1010 return thread->renameTable[reg_idx]->readIntResult();
1013 template <class Impl>
1015 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width)
1017 int idx = reg_idx + TheISA::FP_Base_DepTag;
1020 return thread->renameTable[idx]->readFloatResult();
1022 return thread->renameTable[idx]->readDoubleResult();
1024 panic("Unsupported width!");
1029 template <class Impl>
1031 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
1033 int idx = reg_idx + TheISA::FP_Base_DepTag;
1034 return thread->renameTable[idx]->readFloatResult();
1037 template <class Impl>
1039 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width)
1041 int idx = reg_idx + TheISA::FP_Base_DepTag;
1042 return thread->renameTable[idx]->readIntResult();
1045 template <class Impl>
1047 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
1049 int idx = reg_idx + TheISA::FP_Base_DepTag;
1050 return thread->renameTable[idx]->readIntResult();
1053 template <class Impl>
1055 OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
1057 thread->renameTable[reg_idx]->setIntResult(val);
1059 if (!thread->inSyscall) {
1060 cpu->squashFromTC();
1064 template <class Impl>
1066 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width)
1068 int idx = reg_idx + TheISA::FP_Base_DepTag;
1071 panic("Unimplemented!");
1074 thread->renameTable[idx]->setDoubleResult(val);
1077 panic("Unsupported width!");
1080 if (!thread->inSyscall) {
1081 cpu->squashFromTC();
1085 template <class Impl>
1087 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
1089 int idx = reg_idx + TheISA::FP_Base_DepTag;
1091 thread->renameTable[idx]->setDoubleResult(val);
1093 if (!thread->inSyscall) {
1094 cpu->squashFromTC();
1098 template <class Impl>
1100 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val,
1103 panic("Unimplemented!");
1106 template <class Impl>
1108 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
1110 panic("Unimplemented!");
1113 template <class Impl>
1115 OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
1118 cpu->frontEnd->setPC(val);
1120 if (!thread->inSyscall) {
1121 cpu->squashFromTC();
1125 template <class Impl>
1127 OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
1129 thread->nextPC = val;
1130 cpu->frontEnd->setNextPC(val);
1132 if (!thread->inSyscall) {
1133 cpu->squashFromTC();
1137 template <class Impl>
1139 OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
1141 return thread->miscRegFile.readReg(misc_reg);
1144 template <class Impl>
1146 OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg)
1148 return thread->miscRegFile.readRegWithEffect(misc_reg, this);
1151 template <class Impl>
1153 OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
1155 // Needs to setup a squash event unless we're in syscall mode
1156 thread->miscRegFile.setReg(misc_reg, val);
1158 if (!thread->inSyscall) {
1159 cpu->squashFromTC();
1163 template <class Impl>
1165 OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
1167 // Needs to setup a squash event unless we're in syscall mode
1168 thread->miscRegFile.setRegWithEffect(misc_reg, val, this);
1170 if (!thread->inSyscall) {
1171 cpu->squashFromTC();