src/cpu/ozone/cpu_impl.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  *          Nathan Binkert
  30  */
  31
  32 #include "config/full_system.hh"
  33 #include "config/use_checker.hh"
  34
  35 #include "arch/isa_traits.hh" // For MachInst
  36 #include "base/trace.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/simple_thread.hh"
  39 #include "cpu/thread_context.hh"
  40 #include "cpu/exetrace.hh"
  41 #include "cpu/ozone/cpu.hh"
  42 #include "cpu/quiesce_event.hh"
  43 #include "cpu/static_inst.hh"
  44 #include "sim/sim_object.hh"
  45 #include "sim/stats.hh"
  46
  47 #if FULL_SYSTEM
  48 #include "arch/faults.hh"
  49 #include "arch/alpha/osfpal.hh"
  50 #include "arch/tlb.hh"
  51 #include "arch/types.hh"
  52 #include "arch/kernel_stats.hh"
  53 #include "arch/vtophys.hh"
  54 #include "base/callback.hh"
  55 #include "cpu/profile.hh"
  56 #include "sim/faults.hh"
  57 #include "sim/sim_events.hh"
  58 #include "sim/sim_exit.hh"
  59 #include "sim/system.hh"
  60 #else // !FULL_SYSTEM
  61 #include "sim/process.hh"
  62 #endif // FULL_SYSTEM
  63
  64 #if USE_CHECKER
  65 #include "cpu/checker/thread_context.hh"
  66 #endif
  67
  68 using namespace TheISA;
  69
  70 template <class Impl>
  71 OzoneCPU<Impl>::TickEvent::TickEvent(OzoneCPU *c, int w)
  72     : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
  73 {
  74 }
  75
  76 template <class Impl>
  77 void
  78 OzoneCPU<Impl>::TickEvent::process()
  79 {
  80     cpu->tick();
  81 }
  82
  83 template <class Impl>
  84 const char *
  85 OzoneCPU<Impl>::TickEvent::description() const
  86 {
  87     return "OzoneCPU tick";
  88 }
  89
  90 template <class Impl>
  91 OzoneCPU<Impl>::OzoneCPU(Params *p)
  92 #if FULL_SYSTEM
  93     : BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
  94 #else
  95     : BaseCPU(p), thread(this, 0, p->workload[0], 0),
  96       tickEvent(this, p->width),
  97 #endif
  98       comm(5, 5)
  99 {
 100     frontEnd = new FrontEnd(p);
 101     backEnd = new BackEnd(p);
 102
 103     _status = Idle;
 104
 105     if (p->checker) {
 106 #if USE_CHECKER
 107         BaseCPU *temp_checker = p->checker;
 108         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
 109 #if FULL_SYSTEM
 110         checker->setSystem(p->system);
 111 #endif
 112         checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
 113         thread.tc = checkerTC;
 114         tc = checkerTC;
 115 #else
 116         panic("Checker enabled but not compiled in!");
 117 #endif
 118     } else {
 119         // If checker is not being used, then the xcProxy points
 120         // directly to the CPU's ExecContext.
 121         checker = NULL;
 122         thread.tc = &ozoneTC;
 123         tc = &ozoneTC;
 124     }
 125
 126     ozoneTC.cpu = this;
 127     ozoneTC.thread = &thread;
 128
 129     thread.inSyscall = false;
 130
 131     thread.setStatus(ThreadContext::Suspended);
 132     itb = p->itb;
 133     dtb = p->dtb;
 134 #if FULL_SYSTEM
 135     // Setup thread state stuff.
 136     thread.cpu = this;
 137     thread.setTid(0);
 138
 139     thread.quiesceEvent = new EndQuiesceEvent(tc);
 140
 141     system = p->system;
 142     physmem = p->system->physmem;
 143
 144     if (p->profile) {
 145         thread.profile = new FunctionProfile(p->system->kernelSymtab);
 146         // @todo: This might be better as an ThreadContext instead of OzoneTC
 147         Callback *cb =
 148             new MakeCallback<OzoneTC,
 149             &OzoneTC::dumpFuncProfile>(&ozoneTC);
 150         registerExitCallback(cb);
 151     }
 152
 153     // let's fill with a dummy node for now so we don't get a segfault
 154     // on the first cycle when there's no node available.
 155     static ProfileNode dummyNode;
 156     thread.profileNode = &dummyNode;
 157     thread.profilePC = 3;
 158 #else
 159     thread.cpu = this;
 160 #endif // !FULL_SYSTEM
 161
 162     numInst = 0;
 163     startNumInst = 0;
 164
 165     threadContexts.push_back(tc);
 166
 167     frontEnd->setCPU(this);
 168     backEnd->setCPU(this);
 169
 170     frontEnd->setTC(tc);
 171     backEnd->setTC(tc);
 172
 173     frontEnd->setThreadState(&thread);
 174     backEnd->setThreadState(&thread);
 175
 176     frontEnd->setCommBuffer(&comm);
 177     backEnd->setCommBuffer(&comm);
 178
 179     frontEnd->setBackEnd(backEnd);
 180     backEnd->setFrontEnd(frontEnd);
 181
 182     globalSeqNum = 1;
 183
 184     lockFlag = 0;
 185
 186     // Setup rename table, initializing all values to ready.
 187     for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
 188         thread.renameTable[i] = new DynInst(this);
 189         thread.renameTable[i]->setResultReady();
 190     }
 191
 192     frontEnd->renameTable.copyFrom(thread.renameTable);
 193     backEnd->renameTable.copyFrom(thread.renameTable);
 194
 195 #if FULL_SYSTEM
 196     Port *mem_port;
 197     FunctionalPort *phys_port;
 198     VirtualPort *virt_port;
 199     phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
 200                                             name(), 0));
 201     mem_port = system->physmem->getPort("functional");
 202     mem_port->setPeer(phys_port);
 203     phys_port->setPeer(mem_port);
 204
 205     virt_port = new VirtualPort(csprintf("%s-%d-vport",
 206                                          name(), 0));
 207     mem_port = system->physmem->getPort("functional");
 208     mem_port->setPeer(virt_port);
 209     virt_port->setPeer(mem_port);
 210
 211     thread.setPhysPort(phys_port);
 212     thread.setVirtPort(virt_port);
 213 #endif
 214
 215     DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
 216 }
 217
 218 template <class Impl>
 219 OzoneCPU<Impl>::~OzoneCPU()
 220 {
 221 }
 222
 223 template <class Impl>
 224 void
 225 OzoneCPU<Impl>::switchOut()
 226 {
 227     BaseCPU::switchOut();
 228     switchCount = 0;
 229     // Front end needs state from back end, so switch out the back end first.
 230     backEnd->switchOut();
 231     frontEnd->switchOut();
 232 }
 233
 234 template <class Impl>
 235 void
 236 OzoneCPU<Impl>::signalSwitched()
 237 {
 238     // Only complete the switchout when both the front end and back
 239     // end have signalled they are ready to switch.
 240     if (++switchCount == 2) {
 241         backEnd->doSwitchOut();
 242         frontEnd->doSwitchOut();
 243 #if USE_CHECKER
 244         if (checker)
 245             checker->switchOut();
 246 #endif
 247
 248         _status = SwitchedOut;
 249 #ifndef NDEBUG
 250         // Loop through all registers
 251         for (int i = 0; i < AlphaISA::TotalNumRegs; ++i) {
 252             assert(thread.renameTable[i] == frontEnd->renameTable[i]);
 253
 254             assert(thread.renameTable[i] == backEnd->renameTable[i]);
 255
 256             DPRINTF(OzoneCPU, "Checking if register %i matches.\n", i);
 257         }
 258 #endif
 259
 260         if (tickEvent.scheduled())
 261             tickEvent.squash();
 262     }
 263     assert(switchCount <= 2);
 264 }
 265
 266 template <class Impl>
 267 void
 268 OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
 269 {
 270     BaseCPU::takeOverFrom(oldCPU);
 271
 272     thread.trapPending = false;
 273     thread.inSyscall = false;
 274
 275     backEnd->takeOverFrom();
 276     frontEnd->takeOverFrom();
 277     frontEnd->renameTable.copyFrom(thread.renameTable);
 278     backEnd->renameTable.copyFrom(thread.renameTable);
 279     assert(!tickEvent.scheduled());
 280
 281 #ifndef NDEBUG
 282     // Check rename table.
 283     for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
 284         assert(thread.renameTable[i]->isResultReady());
 285     }
 286 #endif
 287
 288     // @todo: Fix hardcoded number
 289     // Clear out any old information in time buffer.
 290     for (int i = 0; i < 15; ++i) {
 291         comm.advance();
 292     }
 293
 294     // if any of this CPU's ThreadContexts are active, mark the CPU as
 295     // running and schedule its tick event.
 296     for (int i = 0; i < threadContexts.size(); ++i) {
 297         ThreadContext *tc = threadContexts[i];
 298         if (tc->status() == ThreadContext::Active &&
 299             _status != Running) {
 300             _status = Running;
 301             tickEvent.schedule(curTick);
 302         }
 303     }
 304     // Nothing running, change status to reflect that we're no longer
 305     // switched out.
 306     if (_status == SwitchedOut) {
 307         _status = Idle;
 308     }
 309 }
 310
 311 template <class Impl>
 312 void
 313 OzoneCPU<Impl>::activateContext(int thread_num, int delay)
 314 {
 315     // Eventually change this in SMT.
 316     assert(thread_num == 0);
 317
 318     assert(_status == Idle);
 319     notIdleFraction++;
 320     scheduleTickEvent(delay);
 321     _status = Running;
 322 #if FULL_SYSTEM
 323     if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
 324         thread.quiesceEvent->deschedule();
 325 #endif
 326     thread.setStatus(ThreadContext::Active);
 327     frontEnd->wakeFromQuiesce();
 328 }
 329
 330 template <class Impl>
 331 void
 332 OzoneCPU<Impl>::suspendContext(int thread_num)
 333 {
 334     // Eventually change this in SMT.
 335     assert(thread_num == 0);
 336     // @todo: Figure out how to initially set the status properly so
 337     // this is running.
 338 //    assert(_status == Running);
 339     notIdleFraction--;
 340     unscheduleTickEvent();
 341     _status = Idle;
 342 }
 343
 344 template <class Impl>
 345 void
 346 OzoneCPU<Impl>::deallocateContext(int thread_num, int delay)
 347 {
 348     // for now, these are equivalent
 349     suspendContext(thread_num);
 350 }
 351
 352 template <class Impl>
 353 void
 354 OzoneCPU<Impl>::haltContext(int thread_num)
 355 {
 356     // for now, these are equivalent
 357     suspendContext(thread_num);
 358 }
 359
 360 template <class Impl>
 361 void
 362 OzoneCPU<Impl>::regStats()
 363 {
 364     using namespace Stats;
 365
 366     BaseCPU::regStats();
 367
 368     thread.numInsts
 369         .name(name() + ".num_insts")
 370         .desc("Number of instructions executed")
 371         ;
 372
 373     thread.numMemRefs
 374         .name(name() + ".num_refs")
 375         .desc("Number of memory references")
 376         ;
 377
 378     notIdleFraction
 379         .name(name() + ".not_idle_fraction")
 380         .desc("Percentage of non-idle cycles")
 381         ;
 382
 383     idleFraction
 384         .name(name() + ".idle_fraction")
 385         .desc("Percentage of idle cycles")
 386         ;
 387
 388     quiesceCycles
 389         .name(name() + ".quiesce_cycles")
 390         .desc("Number of cycles spent in quiesce")
 391         ;
 392
 393     idleFraction = constant(1.0) - notIdleFraction;
 394
 395     frontEnd->regStats();
 396     backEnd->regStats();
 397 }
 398
 399 template <class Impl>
 400 void
 401 OzoneCPU<Impl>::resetStats()
 402 {
 403 //    startNumInst = numInst;
 404     notIdleFraction = (_status != Idle);
 405 }
 406
 407 template <class Impl>
 408 void
 409 OzoneCPU<Impl>::init()
 410 {
 411     BaseCPU::init();
 412
 413     // Mark this as in syscall so it won't need to squash
 414     thread.inSyscall = true;
 415 #if FULL_SYSTEM
 416     for (int i = 0; i < threadContexts.size(); ++i) {
 417         ThreadContext *tc = threadContexts[i];
 418
 419         // initialize CPU, including PC
 420         TheISA::initCPU(tc, tc->readCpuId());
 421     }
 422 #endif
 423     frontEnd->renameTable.copyFrom(thread.renameTable);
 424     backEnd->renameTable.copyFrom(thread.renameTable);
 425
 426     thread.inSyscall = false;
 427 }
 428
 429 template <class Impl>
 430 Port *
 431 OzoneCPU<Impl>::getPort(const std::string &if_name, int idx)
 432 {
 433     if (if_name == "dcache_port")
 434         return backEnd->getDcachePort();
 435     else if (if_name == "icache_port")
 436         return frontEnd->getIcachePort();
 437     else
 438         panic("No Such Port\n");
 439 }
 440
 441 template <class Impl>
 442 void
 443 OzoneCPU<Impl>::serialize(std::ostream &os)
 444 {
 445     BaseCPU::serialize(os);
 446     SERIALIZE_ENUM(_status);
 447     nameOut(os, csprintf("%s.tc", name()));
 448     ozoneTC.serialize(os);
 449     nameOut(os, csprintf("%s.tickEvent", name()));
 450     tickEvent.serialize(os);
 451
 452     // Use SimpleThread's ability to checkpoint to make it easier to
 453     // write out the registers.  Also make this static so it doesn't
 454     // get instantiated multiple times (causes a panic in statistics).
 455     static SimpleThread temp;
 456
 457     nameOut(os, csprintf("%s.xc.0", name()));
 458     temp.copyTC(thread.getTC());
 459     temp.serialize(os);
 460 }
 461
 462 template <class Impl>
 463 void
 464 OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
 465 {
 466     BaseCPU::unserialize(cp, section);
 467     UNSERIALIZE_ENUM(_status);
 468     ozoneTC.unserialize(cp, csprintf("%s.tc", section));
 469     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 470
 471     // Use SimpleThread's ability to checkpoint to make it easier to
 472     // read in the registers.  Also make this static so it doesn't
 473     // get instantiated multiple times (causes a panic in statistics).
 474     static SimpleThread temp;
 475
 476     temp.copyTC(thread.getTC());
 477     temp.unserialize(cp, csprintf("%s.xc.0", section));
 478     thread.getTC()->copyArchRegs(temp.getTC());
 479 }
 480
 481 template <class Impl>
 482 Fault
 483 OzoneCPU<Impl>::copySrcTranslate(Addr src)
 484 {
 485     panic("Copy not implemented!\n");
 486     return NoFault;
 487 #if 0
 488     static bool no_warn = true;
 489     int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
 490     // Only support block sizes of 64 atm.
 491     assert(blk_size == 64);
 492     int offset = src & (blk_size - 1);
 493
 494     // Make sure block doesn't span page
 495     if (no_warn &&
 496         (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
 497         (src >> 40) != 0xfffffc) {
 498         warn("Copied block source spans pages %x.", src);
 499         no_warn = false;
 500     }
 501
 502     memReq->reset(src & ~(blk_size - 1), blk_size);
 503
 504     // translate to physical address
 505     Fault fault = tc->translateDataReadReq(memReq);
 506
 507     assert(fault != Alignment_Fault);
 508
 509     if (fault == NoFault) {
 510         tc->copySrcAddr = src;
 511         tc->copySrcPhysAddr = memReq->paddr + offset;
 512     } else {
 513         tc->copySrcAddr = 0;
 514         tc->copySrcPhysAddr = 0;
 515     }
 516     return fault;
 517 #endif
 518 }
 519
 520 template <class Impl>
 521 Fault
 522 OzoneCPU<Impl>::copy(Addr dest)
 523 {
 524     panic("Copy not implemented!\n");
 525     return NoFault;
 526 #if 0
 527     static bool no_warn = true;
 528     int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
 529     // Only support block sizes of 64 atm.
 530     assert(blk_size == 64);
 531     uint8_t data[blk_size];
 532     //assert(tc->copySrcAddr);
 533     int offset = dest & (blk_size - 1);
 534
 535     // Make sure block doesn't span page
 536     if (no_warn &&
 537         (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
 538         (dest >> 40) != 0xfffffc) {
 539         no_warn = false;
 540         warn("Copied block destination spans pages %x. ", dest);
 541     }
 542
 543     memReq->reset(dest & ~(blk_size -1), blk_size);
 544     // translate to physical address
 545     Fault fault = tc->translateDataWriteReq(memReq);
 546
 547     assert(fault != Alignment_Fault);
 548
 549     if (fault == NoFault) {
 550         Addr dest_addr = memReq->paddr + offset;
 551         // Need to read straight from memory since we have more than 8 bytes.
 552         memReq->paddr = tc->copySrcPhysAddr;
 553         tc->mem->read(memReq, data);
 554         memReq->paddr = dest_addr;
 555         tc->mem->write(memReq, data);
 556         if (dcacheInterface) {
 557             memReq->cmd = Copy;
 558             memReq->completionEvent = NULL;
 559             memReq->paddr = tc->copySrcPhysAddr;
 560             memReq->dest = dest_addr;
 561             memReq->size = 64;
 562             memReq->time = curTick;
 563             dcacheInterface->access(memReq);
 564         }
 565     }
 566     return fault;
 567 #endif
 568 }
 569
 570 #if FULL_SYSTEM
 571 template <class Impl>
 572 Addr
 573 OzoneCPU<Impl>::dbg_vtophys(Addr addr)
 574 {
 575     return vtophys(tc, addr);
 576 }
 577 #endif // FULL_SYSTEM
 578
 579 #if FULL_SYSTEM
 580 template <class Impl>
 581 void
 582 OzoneCPU<Impl>::post_interrupt(int int_num, int index)
 583 {
 584     BaseCPU::post_interrupt(int_num, index);
 585
 586     if (_status == Idle) {
 587         DPRINTF(IPI,"Suspended Processor awoke\n");
 588 //      thread.activate();
 589         // Hack for now.  Otherwise might have to go through the tc, or
 590         // I need to figure out what's the right thing to call.
 591         activateContext(thread.readTid(), 1);
 592     }
 593 }
 594 #endif // FULL_SYSTEM
 595
 596 /* start simulation, program loaded, processor precise state initialized */
 597 template <class Impl>
 598 void
 599 OzoneCPU<Impl>::tick()
 600 {
 601     DPRINTF(OzoneCPU, "\n\nOzoneCPU: Ticking cpu.\n");
 602
 603     _status = Running;
 604     thread.renameTable[ZeroReg]->setIntResult(0);
 605     thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
 606         setDoubleResult(0.0);
 607
 608     comm.advance();
 609     frontEnd->tick();
 610     backEnd->tick();
 611
 612     // check for instruction-count-based events
 613     comInstEventQueue[0]->serviceEvents(numInst);
 614
 615     if (!tickEvent.scheduled() && _status == Running)
 616         tickEvent.schedule(curTick + ticks(1));
 617 }
 618
 619 template <class Impl>
 620 void
 621 OzoneCPU<Impl>::squashFromTC()
 622 {
 623     thread.inSyscall = true;
 624     backEnd->generateTCEvent();
 625 }
 626
 627 #if !FULL_SYSTEM
 628 template <class Impl>
 629 void
 630 OzoneCPU<Impl>::syscall(uint64_t &callnum)
 631 {
 632     // Not sure this copy is needed, depending on how the TC proxy is made.
 633     thread.renameTable.copyFrom(backEnd->renameTable);
 634
 635     thread.inSyscall = true;
 636
 637     thread.funcExeInst++;
 638
 639     DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst);
 640
 641     thread.process->syscall(callnum, tc);
 642
 643     thread.funcExeInst--;
 644
 645     thread.inSyscall = false;
 646
 647     frontEnd->renameTable.copyFrom(thread.renameTable);
 648     backEnd->renameTable.copyFrom(thread.renameTable);
 649 }
 650
 651 template <class Impl>
 652 void
 653 OzoneCPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
 654 {
 655     // check for error condition.  Alpha syscall convention is to
 656     // indicate success/failure in reg a3 (r19) and put the
 657     // return value itself in the standard return value reg (v0).
 658     if (return_value.successful()) {
 659         // no error
 660         thread.renameTable[SyscallSuccessReg]->setIntResult(0);
 661         thread.renameTable[ReturnValueReg]->setIntResult(
 662             return_value.value());
 663     } else {
 664         // got an error, return details
 665         thread.renameTable[SyscallSuccessReg]->setIntResult((IntReg) -1);
 666         thread.renameTable[ReturnValueReg]->setIntResult(
 667             -return_value.value());
 668     }
 669 }
 670 #else
 671 template <class Impl>
 672 Fault
 673 OzoneCPU<Impl>::hwrei()
 674 {
 675     // Need to move this to ISA code
 676     // May also need to make this per thread
 677
 678     lockFlag = false;
 679     lockAddrList.clear();
 680     thread.kernelStats->hwrei();
 681
 682     // FIXME: XXX check for interrupts? XXX
 683     return NoFault;
 684 }
 685
 686 template <class Impl>
 687 void
 688 OzoneCPU<Impl>::processInterrupts()
 689 {
 690     // Check for interrupts here.  For now can copy the code that
 691     // exists within isa_fullsys_traits.hh.  Also assume that thread 0
 692     // is the one that handles the interrupts.
 693
 694     // Check if there are any outstanding interrupts
 695     //Handle the interrupts
 696     Fault interrupt = this->interrupts.getInterrupt(thread.getTC());
 697
 698     if (interrupt != NoFault) {
 699         this->interrupts.updateIntrInfo(thread.getTC());
 700         interrupt->invoke(thread.getTC());
 701     }
 702 }
 703
 704 template <class Impl>
 705 bool
 706 OzoneCPU<Impl>::simPalCheck(int palFunc)
 707 {
 708     // Need to move this to ISA code
 709     // May also need to make this per thread
 710     thread.kernelStats->callpal(palFunc, tc);
 711
 712     switch (palFunc) {
 713       case PAL::halt:
 714         haltContext(thread.readTid());
 715         if (--System::numSystemsRunning == 0)
 716             exitSimLoop("all cpus halted");
 717         break;
 718
 719       case PAL::bpt:
 720       case PAL::bugchk:
 721         if (system->breakpoint())
 722             return false;
 723         break;
 724     }
 725
 726     return true;
 727 }
 728 #endif
 729
 730 template <class Impl>
 731 BaseCPU *
 732 OzoneCPU<Impl>::OzoneTC::getCpuPtr()
 733 {
 734     return cpu;
 735 }
 736
 737 template <class Impl>
 738 void
 739 OzoneCPU<Impl>::OzoneTC::setCpuId(int id)
 740 {
 741     cpu->cpuId = id;
 742     thread->setCpuId(id);
 743 }
 744
 745 #if FULL_SYSTEM
 746 template <class Impl>
 747 void
 748 OzoneCPU<Impl>::OzoneTC::delVirtPort(VirtualPort *vp)
 749 {
 750     delete vp;
 751 }
 752 #endif
 753
 754 template <class Impl>
 755 void
 756 OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
 757 {
 758     thread->setStatus(new_status);
 759 }
 760
 761 template <class Impl>
 762 void
 763 OzoneCPU<Impl>::OzoneTC::activate(int delay)
 764 {
 765     cpu->activateContext(thread->readTid(), delay);
 766 }
 767
 768 /// Set the status to Suspended.
 769 template <class Impl>
 770 void
 771 OzoneCPU<Impl>::OzoneTC::suspend()
 772 {
 773     cpu->suspendContext(thread->readTid());
 774 }
 775
 776 /// Set the status to Unallocated.
 777 template <class Impl>
 778 void
 779 OzoneCPU<Impl>::OzoneTC::deallocate(int delay)
 780 {
 781     cpu->deallocateContext(thread->readTid(), delay);
 782 }
 783
 784 /// Set the status to Halted.
 785 template <class Impl>
 786 void
 787 OzoneCPU<Impl>::OzoneTC::halt()
 788 {
 789     cpu->haltContext(thread->readTid());
 790 }
 791
 792 #if FULL_SYSTEM
 793 template <class Impl>
 794 void
 795 OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
 796 {
 797     thread->dumpFuncProfile();
 798 }
 799 #endif
 800
 801 template <class Impl>
 802 void
 803 OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
 804 {
 805     // some things should already be set up
 806 #if FULL_SYSTEM
 807     assert(getSystemPtr() == old_context->getSystemPtr());
 808 #else
 809     assert(getProcessPtr() == old_context->getProcessPtr());
 810 #endif
 811
 812     // copy over functional state
 813     setStatus(old_context->status());
 814     copyArchRegs(old_context);
 815     setCpuId(old_context->readCpuId());
 816
 817     thread->setInst(old_context->getInst());
 818 #if !FULL_SYSTEM
 819     setFuncExeInst(old_context->readFuncExeInst());
 820 #else
 821     EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
 822     if (other_quiesce) {
 823         // Point the quiesce event's TC at this TC so that it wakes up
 824         // the proper CPU.
 825         other_quiesce->tc = this;
 826     }
 827     if (thread->quiesceEvent) {
 828         thread->quiesceEvent->tc = this;
 829     }
 830
 831     // Copy kernel stats pointer from old context.
 832     thread->kernelStats = old_context->getKernelStats();
 833 //    storeCondFailures = 0;
 834     cpu->lockFlag = false;
 835 #endif
 836
 837     old_context->setStatus(ThreadContext::Unallocated);
 838 }
 839
 840 template <class Impl>
 841 void
 842 OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
 843 {
 844 #if FULL_SYSTEM
 845     thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
 846     thread->kernelStats->regStats(name + ".kern");
 847 #endif
 848 }
 849
 850 template <class Impl>
 851 void
 852 OzoneCPU<Impl>::OzoneTC::serialize(std::ostream &os)
 853 {
 854     // Once serialization is added, serialize the quiesce event and
 855     // kernel stats.  Will need to make sure there aren't multiple
 856     // things that serialize them.
 857 }
 858
 859 template <class Impl>
 860 void
 861 OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string &section)
 862 { }
 863
 864 #if FULL_SYSTEM
 865 template <class Impl>
 866 EndQuiesceEvent *
 867 OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
 868 {
 869     return thread->quiesceEvent;
 870 }
 871
 872 template <class Impl>
 873 Tick
 874 OzoneCPU<Impl>::OzoneTC::readLastActivate()
 875 {
 876     return thread->lastActivate;
 877 }
 878
 879 template <class Impl>
 880 Tick
 881 OzoneCPU<Impl>::OzoneTC::readLastSuspend()
 882 {
 883     return thread->lastSuspend;
 884 }
 885
 886 template <class Impl>
 887 void
 888 OzoneCPU<Impl>::OzoneTC::profileClear()
 889 {
 890     thread->profileClear();
 891 }
 892
 893 template <class Impl>
 894 void
 895 OzoneCPU<Impl>::OzoneTC::profileSample()
 896 {
 897     thread->profileSample();
 898 }
 899 #endif
 900
 901 template <class Impl>
 902 int
 903 OzoneCPU<Impl>::OzoneTC::getThreadNum()
 904 {
 905     return thread->readTid();
 906 }
 907
 908 template <class Impl>
 909 TheISA::MachInst
 910 OzoneCPU<Impl>::OzoneTC::getInst()
 911 {
 912     return thread->getInst();
 913 }
 914
 915 template <class Impl>
 916 void
 917 OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
 918 {
 919     thread->PC = tc->readPC();
 920     thread->nextPC = tc->readNextPC();
 921
 922     cpu->frontEnd->setPC(thread->PC);
 923     cpu->frontEnd->setNextPC(thread->nextPC);
 924
 925     // First loop through the integer registers.
 926     for (int i = 0; i < TheISA::NumIntRegs; ++i) {
 927 /*        DPRINTF(OzoneCPU, "Copying over register %i, had data %lli, "
 928                 "now has data %lli.\n",
 929                 i, thread->renameTable[i]->readIntResult(),
 930                 tc->readIntReg(i));
 931 */
 932         thread->renameTable[i]->setIntResult(tc->readIntReg(i));
 933     }
 934
 935     // Then loop through the floating point registers.
 936     for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
 937         int fp_idx = i + TheISA::FP_Base_DepTag;
 938         thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
 939     }
 940
 941 #if !FULL_SYSTEM
 942     thread->funcExeInst = tc->readFuncExeInst();
 943 #endif
 944
 945     // Need to copy the TC values into the current rename table,
 946     // copy the misc regs.
 947     copyMiscRegs(tc, this);
 948 }
 949
 950 template <class Impl>
 951 void
 952 OzoneCPU<Impl>::OzoneTC::clearArchRegs()
 953 {
 954     panic("Unimplemented!");
 955 }
 956
 957 template <class Impl>
 958 uint64_t
 959 OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx)
 960 {
 961     return thread->renameTable[reg_idx]->readIntResult();
 962 }
 963
 964 template <class Impl>
 965 TheISA::FloatReg
 966 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width)
 967 {
 968     int idx = reg_idx + TheISA::FP_Base_DepTag;
 969     switch(width) {
 970       case 32:
 971         return thread->renameTable[idx]->readFloatResult();
 972       case 64:
 973         return thread->renameTable[idx]->readDoubleResult();
 974       default:
 975         panic("Unsupported width!");
 976         return 0;
 977     }
 978 }
 979
 980 template <class Impl>
 981 double
 982 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
 983 {
 984     int idx = reg_idx + TheISA::FP_Base_DepTag;
 985     return thread->renameTable[idx]->readFloatResult();
 986 }
 987
 988 template <class Impl>
 989 uint64_t
 990 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width)
 991 {
 992     int idx = reg_idx + TheISA::FP_Base_DepTag;
 993     return thread->renameTable[idx]->readIntResult();
 994 }
 995
 996 template <class Impl>
 997 uint64_t
 998 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
 999 {
1000     int idx = reg_idx + TheISA::FP_Base_DepTag;
1001     return thread->renameTable[idx]->readIntResult();
1002 }
1003
1004 template <class Impl>
1005 void
1006 OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
1007 {
1008     thread->renameTable[reg_idx]->setIntResult(val);
1009
1010     if (!thread->inSyscall) {
1011         cpu->squashFromTC();
1012     }
1013 }
1014
1015 template <class Impl>
1016 void
1017 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width)
1018 {
1019     int idx = reg_idx + TheISA::FP_Base_DepTag;
1020     switch(width) {
1021       case 32:
1022         panic("Unimplemented!");
1023         break;
1024       case 64:
1025         thread->renameTable[idx]->setDoubleResult(val);
1026         break;
1027       default:
1028         panic("Unsupported width!");
1029     }
1030
1031     if (!thread->inSyscall) {
1032         cpu->squashFromTC();
1033     }
1034 }
1035
1036 template <class Impl>
1037 void
1038 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
1039 {
1040     int idx = reg_idx + TheISA::FP_Base_DepTag;
1041
1042     thread->renameTable[idx]->setDoubleResult(val);
1043
1044     if (!thread->inSyscall) {
1045         cpu->squashFromTC();
1046     }
1047 }
1048
1049 template <class Impl>
1050 void
1051 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val,
1052                                          int width)
1053 {
1054     panic("Unimplemented!");
1055 }
1056
1057 template <class Impl>
1058 void
1059 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
1060 {
1061     panic("Unimplemented!");
1062 }
1063
1064 template <class Impl>
1065 void
1066 OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
1067 {
1068     thread->PC = val;
1069     cpu->frontEnd->setPC(val);
1070
1071     if (!thread->inSyscall) {
1072         cpu->squashFromTC();
1073     }
1074 }
1075
1076 template <class Impl>
1077 void
1078 OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
1079 {
1080     thread->nextPC = val;
1081     cpu->frontEnd->setNextPC(val);
1082
1083     if (!thread->inSyscall) {
1084         cpu->squashFromTC();
1085     }
1086 }
1087
1088 template <class Impl>
1089 TheISA::MiscReg
1090 OzoneCPU<Impl>::OzoneTC::readMiscRegNoEffect(int misc_reg)
1091 {
1092     return thread->miscRegFile.readRegNoEffect(misc_reg);
1093 }
1094
1095 template <class Impl>
1096 TheISA::MiscReg
1097 OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
1098 {
1099     return thread->miscRegFile.readReg(misc_reg, this);
1100 }
1101
1102 template <class Impl>
1103 void
1104 OzoneCPU<Impl>::OzoneTC::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
1105 {
1106     // Needs to setup a squash event unless we're in syscall mode
1107     thread->miscRegFile.setRegNoEffect(misc_reg, val);
1108
1109     if (!thread->inSyscall) {
1110         cpu->squashFromTC();
1111     }
1112 }
1113
1114 template <class Impl>
1115 void
1116 OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
1117 {
1118     // Needs to setup a squash event unless we're in syscall mode
1119     thread->miscRegFile.setReg(misc_reg, val, this);
1120
1121     if (!thread->inSyscall) {
1122         cpu->squashFromTC();
1123     }
1124 }