2 * Copyright (c) 2006 The Regents of The University of Michigan
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32 #include "config/full_system.hh"
33 #include "config/use_checker.hh"
35 #include "arch/isa_traits.hh" // For MachInst
36 #include "base/trace.hh"
37 #include "cpu/base.hh"
38 #include "cpu/simple_thread.hh"
39 #include "cpu/thread_context.hh"
40 #include "cpu/exetrace.hh"
41 #include "cpu/ozone/cpu.hh"
42 #include "cpu/quiesce_event.hh"
43 #include "cpu/static_inst.hh"
44 #include "sim/sim_object.hh"
45 #include "sim/stats.hh"
48 #include "arch/faults.hh"
49 #include "arch/alpha/osfpal.hh"
50 #include "arch/tlb.hh"
51 #include "arch/types.hh"
52 #include "arch/kernel_stats.hh"
53 #include "arch/vtophys.hh"
54 #include "base/callback.hh"
55 #include "cpu/profile.hh"
56 #include "sim/faults.hh"
57 #include "sim/sim_events.hh"
58 #include "sim/sim_exit.hh"
59 #include "sim/system.hh"
61 #include "sim/process.hh"
65 #include "cpu/checker/thread_context.hh"
68 using namespace TheISA;
71 OzoneCPU<Impl>::TickEvent::TickEvent(OzoneCPU *c, int w)
72 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
78 OzoneCPU<Impl>::TickEvent::process()
85 OzoneCPU<Impl>::TickEvent::description() const
87 return "OzoneCPU tick";
91 OzoneCPU<Impl>::OzoneCPU(Params *p)
93 : BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
95 : BaseCPU(p), thread(this, 0, p->workload[0], 0),
96 tickEvent(this, p->width),
103 frontEnd = new FrontEnd(p);
104 backEnd = new BackEnd(p);
110 BaseCPU *temp_checker = p->checker;
111 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
113 checker->setSystem(p->system);
115 checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
116 thread.tc = checkerTC;
119 panic("Checker enabled but not compiled in!");
122 // If checker is not being used, then the xcProxy points
123 // directly to the CPU's ExecContext.
125 thread.tc = &ozoneTC;
130 ozoneTC.thread = &thread;
132 thread.inSyscall = false;
137 // Setup thread state stuff.
141 thread.quiesceEvent = new EndQuiesceEvent(tc);
144 physmem = p->system->physmem;
147 thread.profile = new FunctionProfile(p->system->kernelSymtab);
148 // @todo: This might be better as an ThreadContext instead of OzoneTC
150 new MakeCallback<OzoneTC,
151 &OzoneTC::dumpFuncProfile>(&ozoneTC);
152 registerExitCallback(cb);
155 // let's fill with a dummy node for now so we don't get a segfault
156 // on the first cycle when there's no node available.
157 static ProfileNode dummyNode;
158 thread.profileNode = &dummyNode;
159 thread.profilePC = 3;
162 #endif // !FULL_SYSTEM
167 threadContexts.push_back(tc);
169 frontEnd->setCPU(this);
170 backEnd->setCPU(this);
175 frontEnd->setThreadState(&thread);
176 backEnd->setThreadState(&thread);
178 frontEnd->setCommBuffer(&comm);
179 backEnd->setCommBuffer(&comm);
181 frontEnd->setBackEnd(backEnd);
182 backEnd->setFrontEnd(frontEnd);
188 // Setup rename table, initializing all values to ready.
189 for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
190 thread.renameTable[i] = new DynInst(this);
191 thread.renameTable[i]->setResultReady();
194 frontEnd->renameTable.copyFrom(thread.renameTable);
195 backEnd->renameTable.copyFrom(thread.renameTable);
199 FunctionalPort *phys_port;
200 VirtualPort *virt_port;
201 phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
203 mem_port = system->physmem->getPort("functional");
204 mem_port->setPeer(phys_port);
205 phys_port->setPeer(mem_port);
207 virt_port = new VirtualPort(csprintf("%s-%d-vport",
209 mem_port = system->physmem->getPort("functional");
210 mem_port->setPeer(virt_port);
211 virt_port->setPeer(mem_port);
213 thread.setPhysPort(phys_port);
214 thread.setVirtPort(virt_port);
217 DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
220 template <class Impl>
221 OzoneCPU<Impl>::~OzoneCPU()
225 template <class Impl>
227 OzoneCPU<Impl>::switchOut()
229 BaseCPU::switchOut();
231 // Front end needs state from back end, so switch out the back end first.
232 backEnd->switchOut();
233 frontEnd->switchOut();
236 template <class Impl>
238 OzoneCPU<Impl>::signalSwitched()
240 // Only complete the switchout when both the front end and back
241 // end have signalled they are ready to switch.
242 if (++switchCount == 2) {
243 backEnd->doSwitchOut();
244 frontEnd->doSwitchOut();
247 checker->switchOut();
250 _status = SwitchedOut;
252 // Loop through all registers
253 for (int i = 0; i < AlphaISA::TotalNumRegs; ++i) {
254 assert(thread.renameTable[i] == frontEnd->renameTable[i]);
256 assert(thread.renameTable[i] == backEnd->renameTable[i]);
258 DPRINTF(OzoneCPU, "Checking if register %i matches.\n", i);
262 if (tickEvent.scheduled())
265 assert(switchCount <= 2);
268 template <class Impl>
270 OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
272 BaseCPU::takeOverFrom(oldCPU);
274 thread.trapPending = false;
275 thread.inSyscall = false;
277 backEnd->takeOverFrom();
278 frontEnd->takeOverFrom();
279 frontEnd->renameTable.copyFrom(thread.renameTable);
280 backEnd->renameTable.copyFrom(thread.renameTable);
281 assert(!tickEvent.scheduled());
284 // Check rename table.
285 for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
286 assert(thread.renameTable[i]->isResultReady());
290 // @todo: Fix hardcoded number
291 // Clear out any old information in time buffer.
292 for (int i = 0; i < 15; ++i) {
296 // if any of this CPU's ThreadContexts are active, mark the CPU as
297 // running and schedule its tick event.
298 for (int i = 0; i < threadContexts.size(); ++i) {
299 ThreadContext *tc = threadContexts[i];
300 if (tc->status() == ThreadContext::Active &&
301 _status != Running) {
303 tickEvent.schedule(curTick);
306 // Nothing running, change status to reflect that we're no longer
308 if (_status == SwitchedOut) {
313 template <class Impl>
315 OzoneCPU<Impl>::activateContext(int thread_num, int delay)
317 // Eventually change this in SMT.
318 assert(thread_num == 0);
320 assert(_status == Idle);
322 scheduleTickEvent(delay);
325 if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
326 thread.quiesceEvent->deschedule();
328 thread.setStatus(ThreadContext::Active);
329 frontEnd->wakeFromQuiesce();
332 template <class Impl>
334 OzoneCPU<Impl>::suspendContext(int thread_num)
336 // Eventually change this in SMT.
337 assert(thread_num == 0);
338 // @todo: Figure out how to initially set the status properly so
340 // assert(_status == Running);
342 unscheduleTickEvent();
346 template <class Impl>
348 OzoneCPU<Impl>::deallocateContext(int thread_num, int delay)
350 // for now, these are equivalent
351 suspendContext(thread_num);
354 template <class Impl>
356 OzoneCPU<Impl>::haltContext(int thread_num)
358 // for now, these are equivalent
359 suspendContext(thread_num);
362 template <class Impl>
364 OzoneCPU<Impl>::regStats()
366 using namespace Stats;
371 .name(name() + ".num_insts")
372 .desc("Number of instructions executed")
376 .name(name() + ".num_refs")
377 .desc("Number of memory references")
381 .name(name() + ".not_idle_fraction")
382 .desc("Percentage of non-idle cycles")
386 .name(name() + ".idle_fraction")
387 .desc("Percentage of idle cycles")
391 .name(name() + ".quiesce_cycles")
392 .desc("Number of cycles spent in quiesce")
395 idleFraction = constant(1.0) - notIdleFraction;
397 frontEnd->regStats();
401 template <class Impl>
403 OzoneCPU<Impl>::resetStats()
405 // startNumInst = numInst;
406 notIdleFraction = (_status != Idle);
409 template <class Impl>
411 OzoneCPU<Impl>::init()
415 // Mark this as in syscall so it won't need to squash
416 thread.inSyscall = true;
418 for (int i = 0; i < threadContexts.size(); ++i) {
419 ThreadContext *tc = threadContexts[i];
421 // initialize CPU, including PC
422 TheISA::initCPU(tc, tc->contextId());
425 frontEnd->renameTable.copyFrom(thread.renameTable);
426 backEnd->renameTable.copyFrom(thread.renameTable);
428 thread.inSyscall = false;
431 template <class Impl>
433 OzoneCPU<Impl>::getPort(const std::string &if_name, int idx)
435 if (if_name == "dcache_port")
436 return backEnd->getDcachePort();
437 else if (if_name == "icache_port")
438 return frontEnd->getIcachePort();
440 panic("No Such Port\n");
443 template <class Impl>
445 OzoneCPU<Impl>::serialize(std::ostream &os)
447 BaseCPU::serialize(os);
448 SERIALIZE_ENUM(_status);
449 nameOut(os, csprintf("%s.tc", name()));
450 ozoneTC.serialize(os);
451 nameOut(os, csprintf("%s.tickEvent", name()));
452 tickEvent.serialize(os);
454 // Use SimpleThread's ability to checkpoint to make it easier to
455 // write out the registers. Also make this static so it doesn't
456 // get instantiated multiple times (causes a panic in statistics).
457 static SimpleThread temp;
459 nameOut(os, csprintf("%s.xc.0", name()));
460 temp.copyTC(thread.getTC());
464 template <class Impl>
466 OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
468 BaseCPU::unserialize(cp, section);
469 UNSERIALIZE_ENUM(_status);
470 ozoneTC.unserialize(cp, csprintf("%s.tc", section));
471 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
473 // Use SimpleThread's ability to checkpoint to make it easier to
474 // read in the registers. Also make this static so it doesn't
475 // get instantiated multiple times (causes a panic in statistics).
476 static SimpleThread temp;
478 temp.copyTC(thread.getTC());
479 temp.unserialize(cp, csprintf("%s.xc.0", section));
480 thread.getTC()->copyArchRegs(temp.getTC());
483 template <class Impl>
485 OzoneCPU<Impl>::copySrcTranslate(Addr src)
487 panic("Copy not implemented!\n");
490 static bool no_warn = true;
491 unsigned blk_size = dcacheInterface ? dcacheInterface->getBlockSize() : 64;
492 // Only support block sizes of 64 atm.
493 assert(blk_size == 64);
494 int offset = src & (blk_size - 1);
496 // Make sure block doesn't span page
498 (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
499 (src >> 40) != 0xfffffc) {
500 warn("Copied block source spans pages %x.", src);
504 memReq->reset(src & ~(blk_size - 1), blk_size);
506 // translate to physical address
507 Fault fault = tc->translateDataReadReq(memReq);
509 assert(fault != Alignment_Fault);
511 if (fault == NoFault) {
512 tc->copySrcAddr = src;
513 tc->copySrcPhysAddr = memReq->paddr + offset;
516 tc->copySrcPhysAddr = 0;
522 template <class Impl>
524 OzoneCPU<Impl>::copy(Addr dest)
526 panic("Copy not implemented!\n");
529 static bool no_warn = true;
530 unsigned blk_size = dcacheInterface ? dcacheInterface->getBlockSize() : 64;
531 // Only support block sizes of 64 atm.
532 assert(blk_size == 64);
533 uint8_t data[blk_size];
534 //assert(tc->copySrcAddr);
535 int offset = dest & (blk_size - 1);
537 // Make sure block doesn't span page
539 (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
540 (dest >> 40) != 0xfffffc) {
542 warn("Copied block destination spans pages %x. ", dest);
545 memReq->reset(dest & ~(blk_size -1), blk_size);
546 // translate to physical address
547 Fault fault = tc->translateDataWriteReq(memReq);
549 assert(fault != Alignment_Fault);
551 if (fault == NoFault) {
552 Addr dest_addr = memReq->paddr + offset;
553 // Need to read straight from memory since we have more than 8 bytes.
554 memReq->paddr = tc->copySrcPhysAddr;
555 tc->mem->read(memReq, data);
556 memReq->paddr = dest_addr;
557 tc->mem->write(memReq, data);
558 if (dcacheInterface) {
560 memReq->completionEvent = NULL;
561 memReq->paddr = tc->copySrcPhysAddr;
562 memReq->dest = dest_addr;
564 memReq->time = curTick;
565 dcacheInterface->access(memReq);
573 template <class Impl>
575 OzoneCPU<Impl>::dbg_vtophys(Addr addr)
577 return vtophys(tc, addr);
579 #endif // FULL_SYSTEM
582 template <class Impl>
584 OzoneCPU<Impl>::wakeup()
586 if (_status == Idle) {
587 DPRINTF(IPI,"Suspended Processor awoke\n");
588 // thread.activate();
589 // Hack for now. Otherwise might have to go through the tc, or
590 // I need to figure out what's the right thing to call.
591 activateContext(thread.threadId(), 1);
594 #endif // FULL_SYSTEM
596 /* start simulation, program loaded, processor precise state initialized */
597 template <class Impl>
599 OzoneCPU<Impl>::tick()
601 DPRINTF(OzoneCPU, "\n\nOzoneCPU: Ticking cpu.\n");
604 thread.renameTable[ZeroReg]->setIntResult(0);
605 thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
606 setDoubleResult(0.0);
612 // check for instruction-count-based events
613 comInstEventQueue[0]->serviceEvents(numInst);
615 if (!tickEvent.scheduled() && _status == Running)
616 tickEvent.schedule(curTick + ticks(1));
619 template <class Impl>
621 OzoneCPU<Impl>::squashFromTC()
623 thread.inSyscall = true;
624 backEnd->generateTCEvent();
628 template <class Impl>
630 OzoneCPU<Impl>::syscall(uint64_t &callnum)
632 // Not sure this copy is needed, depending on how the TC proxy is made.
633 thread.renameTable.copyFrom(backEnd->renameTable);
635 thread.inSyscall = true;
637 thread.funcExeInst++;
639 DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst);
641 thread.process->syscall(callnum, tc);
643 thread.funcExeInst--;
645 thread.inSyscall = false;
647 frontEnd->renameTable.copyFrom(thread.renameTable);
648 backEnd->renameTable.copyFrom(thread.renameTable);
651 template <class Impl>
653 OzoneCPU<Impl>::hwrei()
655 // Need to move this to ISA code
656 // May also need to make this per thread
659 lockAddrList.clear();
660 thread.kernelStats->hwrei();
662 // FIXME: XXX check for interrupts? XXX
666 template <class Impl>
668 OzoneCPU<Impl>::processInterrupts()
670 // Check for interrupts here. For now can copy the code that
671 // exists within isa_fullsys_traits.hh. Also assume that thread 0
672 // is the one that handles the interrupts.
674 // Check if there are any outstanding interrupts
675 //Handle the interrupts
676 Fault interrupt = this->interrupts->getInterrupt(thread.getTC());
678 if (interrupt != NoFault) {
679 this->interrupts->updateIntrInfo(thread.getTC());
680 interrupt->invoke(thread.getTC());
684 template <class Impl>
686 OzoneCPU<Impl>::simPalCheck(int palFunc)
688 // Need to move this to ISA code
689 // May also need to make this per thread
690 thread.kernelStats->callpal(palFunc, tc);
694 haltContext(thread.threadId());
695 if (--System::numSystemsRunning == 0)
696 exitSimLoop("all cpus halted");
701 if (system->breakpoint())
710 template <class Impl>
712 OzoneCPU<Impl>::OzoneTC::getCpuPtr()
717 template <class Impl>
719 OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
721 thread->setStatus(new_status);
724 template <class Impl>
726 OzoneCPU<Impl>::OzoneTC::activate(int delay)
728 cpu->activateContext(thread->threadId(), delay);
731 /// Set the status to Suspended.
732 template <class Impl>
734 OzoneCPU<Impl>::OzoneTC::suspend()
736 cpu->suspendContext(thread->threadId());
739 /// Set the status to Halted.
740 template <class Impl>
742 OzoneCPU<Impl>::OzoneTC::halt()
744 cpu->haltContext(thread->threadId());
748 template <class Impl>
750 OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
752 thread->dumpFuncProfile();
756 template <class Impl>
758 OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
760 // some things should already be set up
762 assert(getSystemPtr() == old_context->getSystemPtr());
764 assert(getProcessPtr() == old_context->getProcessPtr());
767 // copy over functional state
768 setStatus(old_context->status());
769 copyArchRegs(old_context);
770 setCpuId(old_context->cpuId());
771 setContextId(old_context->contextId());
773 thread->setInst(old_context->getInst());
775 setFuncExeInst(old_context->readFuncExeInst());
777 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
779 // Point the quiesce event's TC at this TC so that it wakes up
781 other_quiesce->tc = this;
783 if (thread->quiesceEvent) {
784 thread->quiesceEvent->tc = this;
787 // Copy kernel stats pointer from old context.
788 thread->kernelStats = old_context->getKernelStats();
789 // storeCondFailures = 0;
790 cpu->lockFlag = false;
793 old_context->setStatus(ThreadContext::Halted);
796 template <class Impl>
798 OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
801 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
802 thread->kernelStats->regStats(name + ".kern");
806 template <class Impl>
808 OzoneCPU<Impl>::OzoneTC::serialize(std::ostream &os)
810 // Once serialization is added, serialize the quiesce event and
811 // kernel stats. Will need to make sure there aren't multiple
812 // things that serialize them.
815 template <class Impl>
817 OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string §ion)
821 template <class Impl>
823 OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
825 return thread->quiesceEvent;
828 template <class Impl>
830 OzoneCPU<Impl>::OzoneTC::readLastActivate()
832 return thread->lastActivate;
835 template <class Impl>
837 OzoneCPU<Impl>::OzoneTC::readLastSuspend()
839 return thread->lastSuspend;
842 template <class Impl>
844 OzoneCPU<Impl>::OzoneTC::profileClear()
846 thread->profileClear();
849 template <class Impl>
851 OzoneCPU<Impl>::OzoneTC::profileSample()
853 thread->profileSample();
857 template <class Impl>
859 OzoneCPU<Impl>::OzoneTC::threadId()
861 return thread->threadId();
864 template <class Impl>
866 OzoneCPU<Impl>::OzoneTC::getInst()
868 return thread->getInst();
871 template <class Impl>
873 OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
875 thread->PC = tc->readPC();
876 thread->nextPC = tc->readNextPC();
878 cpu->frontEnd->setPC(thread->PC);
879 cpu->frontEnd->setNextPC(thread->nextPC);
881 // First loop through the integer registers.
882 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
883 /* DPRINTF(OzoneCPU, "Copying over register %i, had data %lli, "
884 "now has data %lli.\n",
885 i, thread->renameTable[i]->readIntResult(),
888 thread->renameTable[i]->setIntResult(tc->readIntReg(i));
891 // Then loop through the floating point registers.
892 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
893 int fp_idx = i + TheISA::FP_Base_DepTag;
894 thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
898 thread->funcExeInst = tc->readFuncExeInst();
901 // Need to copy the TC values into the current rename table,
902 // copy the misc regs.
903 copyMiscRegs(tc, this);
906 template <class Impl>
908 OzoneCPU<Impl>::OzoneTC::clearArchRegs()
910 panic("Unimplemented!");
913 template <class Impl>
915 OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx)
917 return thread->renameTable[reg_idx]->readIntResult();
920 template <class Impl>
922 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width)
924 int idx = reg_idx + TheISA::FP_Base_DepTag;
927 return thread->renameTable[idx]->readFloatResult();
929 return thread->renameTable[idx]->readDoubleResult();
931 panic("Unsupported width!");
936 template <class Impl>
938 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
940 int idx = reg_idx + TheISA::FP_Base_DepTag;
941 return thread->renameTable[idx]->readFloatResult();
944 template <class Impl>
946 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width)
948 int idx = reg_idx + TheISA::FP_Base_DepTag;
949 return thread->renameTable[idx]->readIntResult();
952 template <class Impl>
954 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
956 int idx = reg_idx + TheISA::FP_Base_DepTag;
957 return thread->renameTable[idx]->readIntResult();
960 template <class Impl>
962 OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
964 thread->renameTable[reg_idx]->setIntResult(val);
966 if (!thread->inSyscall) {
971 template <class Impl>
973 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width)
975 int idx = reg_idx + TheISA::FP_Base_DepTag;
978 panic("Unimplemented!");
981 thread->renameTable[idx]->setDoubleResult(val);
984 panic("Unsupported width!");
987 if (!thread->inSyscall) {
992 template <class Impl>
994 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
996 int idx = reg_idx + TheISA::FP_Base_DepTag;
998 thread->renameTable[idx]->setDoubleResult(val);
1000 if (!thread->inSyscall) {
1001 cpu->squashFromTC();
1005 template <class Impl>
1007 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val,
1010 panic("Unimplemented!");
1013 template <class Impl>
1015 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
1017 panic("Unimplemented!");
1020 template <class Impl>
1022 OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
1025 cpu->frontEnd->setPC(val);
1027 if (!thread->inSyscall) {
1028 cpu->squashFromTC();
1032 template <class Impl>
1034 OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
1036 thread->nextPC = val;
1037 cpu->frontEnd->setNextPC(val);
1039 if (!thread->inSyscall) {
1040 cpu->squashFromTC();
1044 template <class Impl>
1046 OzoneCPU<Impl>::OzoneTC::readMiscRegNoEffect(int misc_reg)
1048 return thread->miscRegFile.readRegNoEffect(misc_reg);
1051 template <class Impl>
1053 OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
1055 return thread->miscRegFile.readReg(misc_reg, this);
1058 template <class Impl>
1060 OzoneCPU<Impl>::OzoneTC::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
1062 // Needs to setup a squash event unless we're in syscall mode
1063 thread->miscRegFile.setRegNoEffect(misc_reg, val);
1065 if (!thread->inSyscall) {
1066 cpu->squashFromTC();
1070 template <class Impl>
1072 OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
1074 // Needs to setup a squash event unless we're in syscall mode
1075 thread->miscRegFile.setReg(misc_reg, val, this);
1077 if (!thread->inSyscall) {
1078 cpu->squashFromTC();