2 * Copyright (c) 2006 The Regents of The University of Michigan
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32 #include "config/full_system.hh"
33 #include "config/use_checker.hh"
35 #include "arch/isa_traits.hh" // For MachInst
36 #include "base/trace.hh"
37 #include "cpu/base.hh"
38 #include "cpu/simple_thread.hh"
39 #include "cpu/thread_context.hh"
40 #include "cpu/exetrace.hh"
41 #include "cpu/ozone/cpu.hh"
42 #include "cpu/quiesce_event.hh"
43 #include "cpu/static_inst.hh"
44 #include "sim/sim_object.hh"
45 #include "sim/stats.hh"
48 #include "arch/faults.hh"
49 #include "arch/alpha/osfpal.hh"
50 #include "arch/tlb.hh"
51 #include "arch/types.hh"
52 #include "arch/kernel_stats.hh"
53 #include "arch/vtophys.hh"
54 #include "base/callback.hh"
55 #include "cpu/profile.hh"
56 #include "sim/faults.hh"
57 #include "sim/sim_events.hh"
58 #include "sim/sim_exit.hh"
59 #include "sim/system.hh"
61 #include "sim/process.hh"
65 #include "cpu/checker/thread_context.hh"
68 using namespace TheISA;
71 OzoneCPU<Impl>::TickEvent::TickEvent(OzoneCPU *c, int w)
72 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
78 OzoneCPU<Impl>::TickEvent::process()
85 OzoneCPU<Impl>::TickEvent::description() const
87 return "OzoneCPU tick";
91 OzoneCPU<Impl>::OzoneCPU(Params *p)
93 : BaseCPU(p), thread(this, 0), tickEvent(this, p->width),
95 : BaseCPU(p), thread(this, 0, p->workload[0], 0),
96 tickEvent(this, p->width),
103 frontEnd = new FrontEnd(p);
104 backEnd = new BackEnd(p);
110 BaseCPU *temp_checker = p->checker;
111 checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
113 checker->setSystem(p->system);
115 checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
116 thread.tc = checkerTC;
119 panic("Checker enabled but not compiled in!");
122 // If checker is not being used, then the xcProxy points
123 // directly to the CPU's ExecContext.
125 thread.tc = &ozoneTC;
130 ozoneTC.thread = &thread;
132 thread.inSyscall = false;
134 thread.setStatus(ThreadContext::Suspended);
138 // Setup thread state stuff.
142 thread.quiesceEvent = new EndQuiesceEvent(tc);
145 physmem = p->system->physmem;
148 thread.profile = new FunctionProfile(p->system->kernelSymtab);
149 // @todo: This might be better as an ThreadContext instead of OzoneTC
151 new MakeCallback<OzoneTC,
152 &OzoneTC::dumpFuncProfile>(&ozoneTC);
153 registerExitCallback(cb);
156 // let's fill with a dummy node for now so we don't get a segfault
157 // on the first cycle when there's no node available.
158 static ProfileNode dummyNode;
159 thread.profileNode = &dummyNode;
160 thread.profilePC = 3;
163 #endif // !FULL_SYSTEM
168 threadContexts.push_back(tc);
170 frontEnd->setCPU(this);
171 backEnd->setCPU(this);
176 frontEnd->setThreadState(&thread);
177 backEnd->setThreadState(&thread);
179 frontEnd->setCommBuffer(&comm);
180 backEnd->setCommBuffer(&comm);
182 frontEnd->setBackEnd(backEnd);
183 backEnd->setFrontEnd(frontEnd);
189 // Setup rename table, initializing all values to ready.
190 for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
191 thread.renameTable[i] = new DynInst(this);
192 thread.renameTable[i]->setResultReady();
195 frontEnd->renameTable.copyFrom(thread.renameTable);
196 backEnd->renameTable.copyFrom(thread.renameTable);
200 FunctionalPort *phys_port;
201 VirtualPort *virt_port;
202 phys_port = new FunctionalPort(csprintf("%s-%d-funcport",
204 mem_port = system->physmem->getPort("functional");
205 mem_port->setPeer(phys_port);
206 phys_port->setPeer(mem_port);
208 virt_port = new VirtualPort(csprintf("%s-%d-vport",
210 mem_port = system->physmem->getPort("functional");
211 mem_port->setPeer(virt_port);
212 virt_port->setPeer(mem_port);
214 thread.setPhysPort(phys_port);
215 thread.setVirtPort(virt_port);
218 DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
221 template <class Impl>
222 OzoneCPU<Impl>::~OzoneCPU()
226 template <class Impl>
228 OzoneCPU<Impl>::switchOut()
230 BaseCPU::switchOut();
232 // Front end needs state from back end, so switch out the back end first.
233 backEnd->switchOut();
234 frontEnd->switchOut();
237 template <class Impl>
239 OzoneCPU<Impl>::signalSwitched()
241 // Only complete the switchout when both the front end and back
242 // end have signalled they are ready to switch.
243 if (++switchCount == 2) {
244 backEnd->doSwitchOut();
245 frontEnd->doSwitchOut();
248 checker->switchOut();
251 _status = SwitchedOut;
253 // Loop through all registers
254 for (int i = 0; i < AlphaISA::TotalNumRegs; ++i) {
255 assert(thread.renameTable[i] == frontEnd->renameTable[i]);
257 assert(thread.renameTable[i] == backEnd->renameTable[i]);
259 DPRINTF(OzoneCPU, "Checking if register %i matches.\n", i);
263 if (tickEvent.scheduled())
266 assert(switchCount <= 2);
269 template <class Impl>
271 OzoneCPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
273 BaseCPU::takeOverFrom(oldCPU);
275 thread.trapPending = false;
276 thread.inSyscall = false;
278 backEnd->takeOverFrom();
279 frontEnd->takeOverFrom();
280 frontEnd->renameTable.copyFrom(thread.renameTable);
281 backEnd->renameTable.copyFrom(thread.renameTable);
282 assert(!tickEvent.scheduled());
285 // Check rename table.
286 for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
287 assert(thread.renameTable[i]->isResultReady());
291 // @todo: Fix hardcoded number
292 // Clear out any old information in time buffer.
293 for (int i = 0; i < 15; ++i) {
297 // if any of this CPU's ThreadContexts are active, mark the CPU as
298 // running and schedule its tick event.
299 for (int i = 0; i < threadContexts.size(); ++i) {
300 ThreadContext *tc = threadContexts[i];
301 if (tc->status() == ThreadContext::Active &&
302 _status != Running) {
304 tickEvent.schedule(curTick);
307 // Nothing running, change status to reflect that we're no longer
309 if (_status == SwitchedOut) {
314 template <class Impl>
316 OzoneCPU<Impl>::activateContext(int thread_num, int delay)
318 // Eventually change this in SMT.
319 assert(thread_num == 0);
321 assert(_status == Idle);
323 scheduleTickEvent(delay);
326 if (thread.quiesceEvent && thread.quiesceEvent->scheduled())
327 thread.quiesceEvent->deschedule();
329 thread.setStatus(ThreadContext::Active);
330 frontEnd->wakeFromQuiesce();
333 template <class Impl>
335 OzoneCPU<Impl>::suspendContext(int thread_num)
337 // Eventually change this in SMT.
338 assert(thread_num == 0);
339 // @todo: Figure out how to initially set the status properly so
341 // assert(_status == Running);
343 unscheduleTickEvent();
347 template <class Impl>
349 OzoneCPU<Impl>::deallocateContext(int thread_num, int delay)
351 // for now, these are equivalent
352 suspendContext(thread_num);
355 template <class Impl>
357 OzoneCPU<Impl>::haltContext(int thread_num)
359 // for now, these are equivalent
360 suspendContext(thread_num);
363 template <class Impl>
365 OzoneCPU<Impl>::regStats()
367 using namespace Stats;
372 .name(name() + ".num_insts")
373 .desc("Number of instructions executed")
377 .name(name() + ".num_refs")
378 .desc("Number of memory references")
382 .name(name() + ".not_idle_fraction")
383 .desc("Percentage of non-idle cycles")
387 .name(name() + ".idle_fraction")
388 .desc("Percentage of idle cycles")
392 .name(name() + ".quiesce_cycles")
393 .desc("Number of cycles spent in quiesce")
396 idleFraction = constant(1.0) - notIdleFraction;
398 frontEnd->regStats();
402 template <class Impl>
404 OzoneCPU<Impl>::resetStats()
406 // startNumInst = numInst;
407 notIdleFraction = (_status != Idle);
410 template <class Impl>
412 OzoneCPU<Impl>::init()
416 // Mark this as in syscall so it won't need to squash
417 thread.inSyscall = true;
419 for (int i = 0; i < threadContexts.size(); ++i) {
420 ThreadContext *tc = threadContexts[i];
422 // initialize CPU, including PC
423 TheISA::initCPU(tc, tc->contextId());
426 frontEnd->renameTable.copyFrom(thread.renameTable);
427 backEnd->renameTable.copyFrom(thread.renameTable);
429 thread.inSyscall = false;
432 template <class Impl>
434 OzoneCPU<Impl>::getPort(const std::string &if_name, int idx)
436 if (if_name == "dcache_port")
437 return backEnd->getDcachePort();
438 else if (if_name == "icache_port")
439 return frontEnd->getIcachePort();
441 panic("No Such Port\n");
444 template <class Impl>
446 OzoneCPU<Impl>::serialize(std::ostream &os)
448 BaseCPU::serialize(os);
449 SERIALIZE_ENUM(_status);
450 nameOut(os, csprintf("%s.tc", name()));
451 ozoneTC.serialize(os);
452 nameOut(os, csprintf("%s.tickEvent", name()));
453 tickEvent.serialize(os);
455 // Use SimpleThread's ability to checkpoint to make it easier to
456 // write out the registers. Also make this static so it doesn't
457 // get instantiated multiple times (causes a panic in statistics).
458 static SimpleThread temp;
460 nameOut(os, csprintf("%s.xc.0", name()));
461 temp.copyTC(thread.getTC());
465 template <class Impl>
467 OzoneCPU<Impl>::unserialize(Checkpoint *cp, const std::string §ion)
469 BaseCPU::unserialize(cp, section);
470 UNSERIALIZE_ENUM(_status);
471 ozoneTC.unserialize(cp, csprintf("%s.tc", section));
472 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
474 // Use SimpleThread's ability to checkpoint to make it easier to
475 // read in the registers. Also make this static so it doesn't
476 // get instantiated multiple times (causes a panic in statistics).
477 static SimpleThread temp;
479 temp.copyTC(thread.getTC());
480 temp.unserialize(cp, csprintf("%s.xc.0", section));
481 thread.getTC()->copyArchRegs(temp.getTC());
484 template <class Impl>
486 OzoneCPU<Impl>::copySrcTranslate(Addr src)
488 panic("Copy not implemented!\n");
491 static bool no_warn = true;
492 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
493 // Only support block sizes of 64 atm.
494 assert(blk_size == 64);
495 int offset = src & (blk_size - 1);
497 // Make sure block doesn't span page
499 (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
500 (src >> 40) != 0xfffffc) {
501 warn("Copied block source spans pages %x.", src);
505 memReq->reset(src & ~(blk_size - 1), blk_size);
507 // translate to physical address
508 Fault fault = tc->translateDataReadReq(memReq);
510 assert(fault != Alignment_Fault);
512 if (fault == NoFault) {
513 tc->copySrcAddr = src;
514 tc->copySrcPhysAddr = memReq->paddr + offset;
517 tc->copySrcPhysAddr = 0;
523 template <class Impl>
525 OzoneCPU<Impl>::copy(Addr dest)
527 panic("Copy not implemented!\n");
530 static bool no_warn = true;
531 int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
532 // Only support block sizes of 64 atm.
533 assert(blk_size == 64);
534 uint8_t data[blk_size];
535 //assert(tc->copySrcAddr);
536 int offset = dest & (blk_size - 1);
538 // Make sure block doesn't span page
540 (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
541 (dest >> 40) != 0xfffffc) {
543 warn("Copied block destination spans pages %x. ", dest);
546 memReq->reset(dest & ~(blk_size -1), blk_size);
547 // translate to physical address
548 Fault fault = tc->translateDataWriteReq(memReq);
550 assert(fault != Alignment_Fault);
552 if (fault == NoFault) {
553 Addr dest_addr = memReq->paddr + offset;
554 // Need to read straight from memory since we have more than 8 bytes.
555 memReq->paddr = tc->copySrcPhysAddr;
556 tc->mem->read(memReq, data);
557 memReq->paddr = dest_addr;
558 tc->mem->write(memReq, data);
559 if (dcacheInterface) {
561 memReq->completionEvent = NULL;
562 memReq->paddr = tc->copySrcPhysAddr;
563 memReq->dest = dest_addr;
565 memReq->time = curTick;
566 dcacheInterface->access(memReq);
574 template <class Impl>
576 OzoneCPU<Impl>::dbg_vtophys(Addr addr)
578 return vtophys(tc, addr);
580 #endif // FULL_SYSTEM
583 template <class Impl>
585 OzoneCPU<Impl>::wakeup()
587 if (_status == Idle) {
588 DPRINTF(IPI,"Suspended Processor awoke\n");
589 // thread.activate();
590 // Hack for now. Otherwise might have to go through the tc, or
591 // I need to figure out what's the right thing to call.
592 activateContext(thread.threadId(), 1);
595 #endif // FULL_SYSTEM
597 /* start simulation, program loaded, processor precise state initialized */
598 template <class Impl>
600 OzoneCPU<Impl>::tick()
602 DPRINTF(OzoneCPU, "\n\nOzoneCPU: Ticking cpu.\n");
605 thread.renameTable[ZeroReg]->setIntResult(0);
606 thread.renameTable[ZeroReg+TheISA::FP_Base_DepTag]->
607 setDoubleResult(0.0);
613 // check for instruction-count-based events
614 comInstEventQueue[0]->serviceEvents(numInst);
616 if (!tickEvent.scheduled() && _status == Running)
617 tickEvent.schedule(curTick + ticks(1));
620 template <class Impl>
622 OzoneCPU<Impl>::squashFromTC()
624 thread.inSyscall = true;
625 backEnd->generateTCEvent();
629 template <class Impl>
631 OzoneCPU<Impl>::syscall(uint64_t &callnum)
633 // Not sure this copy is needed, depending on how the TC proxy is made.
634 thread.renameTable.copyFrom(backEnd->renameTable);
636 thread.inSyscall = true;
638 thread.funcExeInst++;
640 DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst);
642 thread.process->syscall(callnum, tc);
644 thread.funcExeInst--;
646 thread.inSyscall = false;
648 frontEnd->renameTable.copyFrom(thread.renameTable);
649 backEnd->renameTable.copyFrom(thread.renameTable);
652 template <class Impl>
654 OzoneCPU<Impl>::hwrei()
656 // Need to move this to ISA code
657 // May also need to make this per thread
660 lockAddrList.clear();
661 thread.kernelStats->hwrei();
663 // FIXME: XXX check for interrupts? XXX
667 template <class Impl>
669 OzoneCPU<Impl>::processInterrupts()
671 // Check for interrupts here. For now can copy the code that
672 // exists within isa_fullsys_traits.hh. Also assume that thread 0
673 // is the one that handles the interrupts.
675 // Check if there are any outstanding interrupts
676 //Handle the interrupts
677 Fault interrupt = this->interrupts->getInterrupt(thread.getTC());
679 if (interrupt != NoFault) {
680 this->interrupts->updateIntrInfo(thread.getTC());
681 interrupt->invoke(thread.getTC());
685 template <class Impl>
687 OzoneCPU<Impl>::simPalCheck(int palFunc)
689 // Need to move this to ISA code
690 // May also need to make this per thread
691 thread.kernelStats->callpal(palFunc, tc);
695 haltContext(thread.threadId());
696 if (--System::numSystemsRunning == 0)
697 exitSimLoop("all cpus halted");
702 if (system->breakpoint())
711 template <class Impl>
713 OzoneCPU<Impl>::OzoneTC::getCpuPtr()
718 template <class Impl>
720 OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
722 thread->setStatus(new_status);
725 template <class Impl>
727 OzoneCPU<Impl>::OzoneTC::activate(int delay)
729 cpu->activateContext(thread->threadId(), delay);
732 /// Set the status to Suspended.
733 template <class Impl>
735 OzoneCPU<Impl>::OzoneTC::suspend()
737 cpu->suspendContext(thread->threadId());
740 /// Set the status to Unallocated.
741 template <class Impl>
743 OzoneCPU<Impl>::OzoneTC::deallocate(int delay)
745 cpu->deallocateContext(thread->threadId(), delay);
748 /// Set the status to Halted.
749 template <class Impl>
751 OzoneCPU<Impl>::OzoneTC::halt()
753 cpu->haltContext(thread->threadId());
757 template <class Impl>
759 OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
761 thread->dumpFuncProfile();
765 template <class Impl>
767 OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
769 // some things should already be set up
771 assert(getSystemPtr() == old_context->getSystemPtr());
773 assert(getProcessPtr() == old_context->getProcessPtr());
776 // copy over functional state
777 setStatus(old_context->status());
778 copyArchRegs(old_context);
779 setCpuId(old_context->cpuId());
780 setContextId(old_context->contextId());
782 thread->setInst(old_context->getInst());
784 setFuncExeInst(old_context->readFuncExeInst());
786 EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
788 // Point the quiesce event's TC at this TC so that it wakes up
790 other_quiesce->tc = this;
792 if (thread->quiesceEvent) {
793 thread->quiesceEvent->tc = this;
796 // Copy kernel stats pointer from old context.
797 thread->kernelStats = old_context->getKernelStats();
798 // storeCondFailures = 0;
799 cpu->lockFlag = false;
802 old_context->setStatus(ThreadContext::Unallocated);
805 template <class Impl>
807 OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
810 thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system);
811 thread->kernelStats->regStats(name + ".kern");
815 template <class Impl>
817 OzoneCPU<Impl>::OzoneTC::serialize(std::ostream &os)
819 // Once serialization is added, serialize the quiesce event and
820 // kernel stats. Will need to make sure there aren't multiple
821 // things that serialize them.
824 template <class Impl>
826 OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string §ion)
830 template <class Impl>
832 OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
834 return thread->quiesceEvent;
837 template <class Impl>
839 OzoneCPU<Impl>::OzoneTC::readLastActivate()
841 return thread->lastActivate;
844 template <class Impl>
846 OzoneCPU<Impl>::OzoneTC::readLastSuspend()
848 return thread->lastSuspend;
851 template <class Impl>
853 OzoneCPU<Impl>::OzoneTC::profileClear()
855 thread->profileClear();
858 template <class Impl>
860 OzoneCPU<Impl>::OzoneTC::profileSample()
862 thread->profileSample();
866 template <class Impl>
868 OzoneCPU<Impl>::OzoneTC::threadId()
870 return thread->threadId();
873 template <class Impl>
875 OzoneCPU<Impl>::OzoneTC::getInst()
877 return thread->getInst();
880 template <class Impl>
882 OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
884 thread->PC = tc->readPC();
885 thread->nextPC = tc->readNextPC();
887 cpu->frontEnd->setPC(thread->PC);
888 cpu->frontEnd->setNextPC(thread->nextPC);
890 // First loop through the integer registers.
891 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
892 /* DPRINTF(OzoneCPU, "Copying over register %i, had data %lli, "
893 "now has data %lli.\n",
894 i, thread->renameTable[i]->readIntResult(),
897 thread->renameTable[i]->setIntResult(tc->readIntReg(i));
900 // Then loop through the floating point registers.
901 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
902 int fp_idx = i + TheISA::FP_Base_DepTag;
903 thread->renameTable[fp_idx]->setIntResult(tc->readFloatRegBits(i));
907 thread->funcExeInst = tc->readFuncExeInst();
910 // Need to copy the TC values into the current rename table,
911 // copy the misc regs.
912 copyMiscRegs(tc, this);
915 template <class Impl>
917 OzoneCPU<Impl>::OzoneTC::clearArchRegs()
919 panic("Unimplemented!");
922 template <class Impl>
924 OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx)
926 return thread->renameTable[reg_idx]->readIntResult();
929 template <class Impl>
931 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width)
933 int idx = reg_idx + TheISA::FP_Base_DepTag;
936 return thread->renameTable[idx]->readFloatResult();
938 return thread->renameTable[idx]->readDoubleResult();
940 panic("Unsupported width!");
945 template <class Impl>
947 OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
949 int idx = reg_idx + TheISA::FP_Base_DepTag;
950 return thread->renameTable[idx]->readFloatResult();
953 template <class Impl>
955 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width)
957 int idx = reg_idx + TheISA::FP_Base_DepTag;
958 return thread->renameTable[idx]->readIntResult();
961 template <class Impl>
963 OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
965 int idx = reg_idx + TheISA::FP_Base_DepTag;
966 return thread->renameTable[idx]->readIntResult();
969 template <class Impl>
971 OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
973 thread->renameTable[reg_idx]->setIntResult(val);
975 if (!thread->inSyscall) {
980 template <class Impl>
982 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width)
984 int idx = reg_idx + TheISA::FP_Base_DepTag;
987 panic("Unimplemented!");
990 thread->renameTable[idx]->setDoubleResult(val);
993 panic("Unsupported width!");
996 if (!thread->inSyscall) {
1001 template <class Impl>
1003 OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
1005 int idx = reg_idx + TheISA::FP_Base_DepTag;
1007 thread->renameTable[idx]->setDoubleResult(val);
1009 if (!thread->inSyscall) {
1010 cpu->squashFromTC();
1014 template <class Impl>
1016 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val,
1019 panic("Unimplemented!");
1022 template <class Impl>
1024 OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
1026 panic("Unimplemented!");
1029 template <class Impl>
1031 OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
1034 cpu->frontEnd->setPC(val);
1036 if (!thread->inSyscall) {
1037 cpu->squashFromTC();
1041 template <class Impl>
1043 OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
1045 thread->nextPC = val;
1046 cpu->frontEnd->setNextPC(val);
1048 if (!thread->inSyscall) {
1049 cpu->squashFromTC();
1053 template <class Impl>
1055 OzoneCPU<Impl>::OzoneTC::readMiscRegNoEffect(int misc_reg)
1057 return thread->miscRegFile.readRegNoEffect(misc_reg);
1060 template <class Impl>
1062 OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
1064 return thread->miscRegFile.readReg(misc_reg, this);
1067 template <class Impl>
1069 OzoneCPU<Impl>::OzoneTC::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
1071 // Needs to setup a squash event unless we're in syscall mode
1072 thread->miscRegFile.setRegNoEffect(misc_reg, val);
1074 if (!thread->inSyscall) {
1075 cpu->squashFromTC();
1079 template <class Impl>
1081 OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
1083 // Needs to setup a squash event unless we're in syscall mode
1084 thread->miscRegFile.setReg(misc_reg, val, this);
1086 if (!thread->inSyscall) {
1087 cpu->squashFromTC();