src/cpu/ozone/dyn_inst.hh

   1 /*
   2  * Copyright (c) 2005-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_DYN_INST_HH__
  32 #define __CPU_OZONE_DYN_INST_HH__
  33
  34 #include "arch/isa_traits.hh"
  35 #include "config/full_system.hh"
  36 #include "cpu/base_dyn_inst.hh"
  37 #include "cpu/ozone/cpu.hh"   // MUST include this
  38 #include "cpu/inst_seq.hh"
  39 //#include "cpu/ozone/simple_impl.hh" // Would be nice to not have to include this
  40 #include "cpu/ozone/ozone_impl.hh"
  41
  42 #include <list>
  43 #include <vector>
  44
  45 template <class Impl>
  46 class OzoneDynInst : public BaseDynInst<Impl>
  47 {
  48   public:
  49     // Typedefs
  50     typedef typename Impl::FullCPU FullCPU;
  51
  52     typedef typename FullCPU::ImplState ImplState;
  53
  54     // Typedef for DynInstPtr.  This is really just a RefCountingPtr<OoODynInst>.
  55     typedef typename Impl::DynInstPtr DynInstPtr;
  56
  57     typedef TheISA::ExtMachInst ExtMachInst;
  58     typedef TheISA::MachInst MachInst;
  59     typedef TheISA::MiscReg MiscReg;
  60     typedef typename std::list<DynInstPtr>::iterator ListIt;
  61
  62     // Note that this is duplicated from the BaseDynInst class; I'm
  63     // simply not sure the enum would carry through so I could use it
  64     // in array declarations in this class.
  65     enum {
  66         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,
  67         MaxInstDestRegs = TheISA::MaxInstDestRegs
  68     };
  69
  70     OzoneDynInst(FullCPU *cpu);
  71
  72     OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
  73                  InstSeqNum seq_num, FullCPU *cpu);
  74
  75     OzoneDynInst(StaticInstPtr inst);
  76
  77     ~OzoneDynInst();
  78
  79     void setSrcInst(DynInstPtr &newSrcInst, int regIdx)
  80     { srcInsts[regIdx] = newSrcInst; }
  81
  82     bool srcInstReady(int regIdx);
  83
  84     void setPrevDestInst(DynInstPtr &oldDestInst, int regIdx)
  85     { prevDestInst[regIdx] = oldDestInst; }
  86
  87     DynInstPtr &getPrevDestInst(int regIdx)
  88     { return prevDestInst[regIdx]; }
  89
  90     void addDependent(DynInstPtr &dependent_inst);
  91
  92     std::vector<DynInstPtr> &getDependents() { return dependents; }
  93     std::vector<DynInstPtr> &getMemDeps() { return memDependents; }
  94     std::list<DynInstPtr> &getMemSrcs() { return srcMemInsts; }
  95
  96     void wakeDependents();
  97
  98     void wakeMemDependents();
  99
 100     void addMemDependent(DynInstPtr &inst) { memDependents.push_back(inst); }
 101
 102     void addSrcMemInst(DynInstPtr &inst) { srcMemInsts.push_back(inst); }
 103
 104     void markMemInstReady(OzoneDynInst<Impl> *inst);
 105
 106     // For now I will remove instructions from the list when they wake
 107     // up.  In the future, you only really need a counter.
 108     bool memDepReady() { return srcMemInsts.empty(); }
 109
 110   private:
 111     void initInstPtrs();
 112
 113     std::vector<DynInstPtr> dependents;
 114
 115     std::vector<DynInstPtr> memDependents;
 116
 117     std::list<DynInstPtr> srcMemInsts;
 118
 119     /** The instruction that produces the value of the source
 120      *  registers.  These may be NULL if the value has already been
 121      *  read from the source instruction.
 122      */
 123     DynInstPtr srcInsts[MaxInstSrcRegs];
 124
 125     /**
 126      *  Previous rename instruction for this destination.
 127      */
 128     DynInstPtr prevDestInst[MaxInstSrcRegs];
 129
 130   public:
 131
 132     Fault initiateAcc();
 133
 134     Fault completeAcc();
 135
 136     // The register accessor methods provide the index of the
 137     // instruction's operand (e.g., 0 or 1), not the architectural
 138     // register index, to simplify the implementation of register
 139     // renaming.  We find the architectural register index by indexing
 140     // into the instruction's own operand index table.  Note that a
 141     // raw pointer to the StaticInst is provided instead of a
 142     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 143     // long as these methods don't copy the pointer into any long-term
 144     // storage (which is pretty hard to imagine they would have reason
 145     // to do).
 146
 147     uint64_t readIntReg(const StaticInst *si, int idx)
 148     {
 149         return srcInsts[idx]->readIntResult();
 150     }
 151
 152     float readFloatRegSingle(const StaticInst *si, int idx)
 153     {
 154         return srcInsts[idx]->readFloatResult();
 155     }
 156
 157     double readFloatRegDouble(const StaticInst *si, int idx)
 158     {
 159         return srcInsts[idx]->readDoubleResult();
 160     }
 161
 162     uint64_t readFloatRegInt(const StaticInst *si, int idx)
 163     {
 164         return srcInsts[idx]->readIntResult();
 165     }
 166
 167     /** @todo: Make results into arrays so they can handle multiple dest
 168      *  registers.
 169      */
 170     void setIntReg(const StaticInst *si, int idx, uint64_t val)
 171     {
 172         BaseDynInst<Impl>::setIntReg(si, idx, val);
 173     }
 174
 175     void setFloatRegSingle(const StaticInst *si, int idx, float val)
 176     {
 177         BaseDynInst<Impl>::setFloatRegSingle(si, idx, val);
 178     }
 179
 180     void setFloatRegDouble(const StaticInst *si, int idx, double val)
 181     {
 182         BaseDynInst<Impl>::setFloatRegDouble(si, idx, val);
 183     }
 184
 185     void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
 186     {
 187         BaseDynInst<Impl>::setFloatRegInt(si, idx, val);
 188     }
 189
 190     void setIntResult(uint64_t result) { this->instResult.integer = result; }
 191     void setDoubleResult(double result) { this->instResult.dbl = result; }
 192
 193     bool srcsReady();
 194     bool eaSrcsReady();
 195
 196     Fault execute();
 197
 198     Fault executeEAComp()
 199     { return NoFault; }
 200
 201     Fault executeMemAcc()
 202     { return this->staticInst->memAccInst()->execute(this, this->traceData); }
 203
 204     void clearDependents();
 205
 206     void clearMemDependents();
 207
 208   public:
 209     // ISA stuff
 210     MiscReg readMiscReg(int misc_reg);
 211
 212     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
 213
 214     Fault setMiscReg(int misc_reg, const MiscReg &val);
 215
 216     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
 217
 218 #if FULL_SYSTEM
 219     Fault hwrei();
 220     int readIntrFlag();
 221     void setIntrFlag(int val);
 222     bool inPalMode();
 223     void trap(Fault fault);
 224     bool simPalCheck(int palFunc);
 225 #else
 226     void syscall();
 227 #endif
 228
 229     ListIt iqIt;
 230     bool iqItValid;
 231 };
 232
 233 #endif // __CPU_OZONE_DYN_INST_HH__