src/cpu/ozone/dyn_inst.hh

   1 /*
   2  * Copyright (c) 2005-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_DYN_INST_HH__
  32 #define __CPU_OZONE_DYN_INST_HH__
  33
  34 #include "arch/isa_traits.hh"
  35 #include "config/full_system.hh"
  36 #include "cpu/base_dyn_inst.hh"
  37 #include "cpu/inst_seq.hh"
  38 #include "cpu/ozone/cpu.hh"   // MUST include this
  39 #include "cpu/ozone/ozone_impl.hh"
  40
  41 #include <list>
  42 #include <vector>
  43
  44 template <class Impl>
  45 class OzoneDynInst : public BaseDynInst<Impl>
  46 {
  47   public:
  48     // Typedefs
  49     typedef typename Impl::OzoneCPU OzoneCPU;
  50
  51     typedef typename OzoneCPU::ImplState ImplState;
  52
  53     // Typedef for DynInstPtr.  This is really just a RefCountingPtr<OoODynInst>.
  54     typedef typename Impl::DynInstPtr DynInstPtr;
  55
  56     typedef TheISA::ExtMachInst ExtMachInst;
  57     typedef TheISA::MachInst MachInst;
  58     typedef TheISA::FloatReg FloatReg;
  59     typedef TheISA::FloatRegBits FloatRegBits;
  60     typedef TheISA::MiscReg MiscReg;
  61     typedef typename std::list<DynInstPtr>::iterator ListIt;
  62
  63     // Note that this is duplicated from the BaseDynInst class; I'm
  64     // simply not sure the enum would carry through so I could use it
  65     // in array declarations in this class.
  66     enum {
  67         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,
  68         MaxInstDestRegs = TheISA::MaxInstDestRegs
  69     };
  70
  71     OzoneDynInst(OzoneCPU *cpu);
  72
  73     OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
  74                  InstSeqNum seq_num, OzoneCPU *cpu);
  75
  76     OzoneDynInst(StaticInstPtr inst);
  77
  78     ~OzoneDynInst();
  79
  80     void setSrcInst(DynInstPtr &newSrcInst, int regIdx)
  81     { srcInsts[regIdx] = newSrcInst; }
  82
  83     bool srcInstReady(int regIdx);
  84
  85     void setPrevDestInst(DynInstPtr &oldDestInst, int regIdx)
  86     { prevDestInst[regIdx] = oldDestInst; }
  87
  88     DynInstPtr &getPrevDestInst(int regIdx)
  89     { return prevDestInst[regIdx]; }
  90
  91     void addDependent(DynInstPtr &dependent_inst);
  92
  93     std::vector<DynInstPtr> &getDependents() { return dependents; }
  94     std::vector<DynInstPtr> &getMemDeps() { return memDependents; }
  95     std::list<DynInstPtr> &getMemSrcs() { return srcMemInsts; }
  96
  97     void wakeDependents();
  98
  99     void wakeMemDependents();
 100
 101     void addMemDependent(DynInstPtr &inst) { memDependents.push_back(inst); }
 102
 103     void addSrcMemInst(DynInstPtr &inst) { srcMemInsts.push_back(inst); }
 104
 105     void markMemInstReady(OzoneDynInst<Impl> *inst);
 106
 107     // For now I will remove instructions from the list when they wake
 108     // up.  In the future, you only really need a counter.
 109     bool memDepReady() { return srcMemInsts.empty(); }
 110
 111   private:
 112     void initInstPtrs();
 113
 114     std::vector<DynInstPtr> dependents;
 115
 116     std::vector<DynInstPtr> memDependents;
 117
 118     std::list<DynInstPtr> srcMemInsts;
 119
 120     /** The instruction that produces the value of the source
 121      *  registers.  These may be NULL if the value has already been
 122      *  read from the source instruction.
 123      */
 124     DynInstPtr srcInsts[MaxInstSrcRegs];
 125
 126     /**
 127      *  Previous rename instruction for this destination.
 128      */
 129     DynInstPtr prevDestInst[MaxInstSrcRegs];
 130
 131   public:
 132
 133     Fault initiateAcc();
 134
 135     Fault completeAcc(Packet *pkt);
 136
 137     // The register accessor methods provide the index of the
 138     // instruction's operand (e.g., 0 or 1), not the architectural
 139     // register index, to simplify the implementation of register
 140     // renaming.  We find the architectural register index by indexing
 141     // into the instruction's own operand index table.  Note that a
 142     // raw pointer to the StaticInst is provided instead of a
 143     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 144     // long as these methods don't copy the pointer into any long-term
 145     // storage (which is pretty hard to imagine they would have reason
 146     // to do).
 147
 148     uint64_t readIntReg(const StaticInst *si, int idx)
 149     {
 150         return srcInsts[idx]->readIntResult();
 151     }
 152
 153     FloatReg readFloatReg(const StaticInst *si, int idx, int width)
 154     {
 155         switch(width) {
 156           case 32:
 157             return srcInsts[idx]->readFloatResult();
 158           case 64:
 159             return srcInsts[idx]->readDoubleResult();
 160           default:
 161             panic("Width not supported");
 162             return 0;
 163         }
 164     }
 165
 166     FloatReg readFloatReg(const StaticInst *si, int idx)
 167     {
 168         return srcInsts[idx]->readFloatResult();
 169     }
 170
 171     FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
 172     {
 173         return srcInsts[idx]->readIntResult();
 174     }
 175
 176     FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
 177     {
 178         return srcInsts[idx]->readIntResult();
 179     }
 180
 181     /** @todo: Make results into arrays so they can handle multiple dest
 182      *  registers.
 183      */
 184     void setIntReg(const StaticInst *si, int idx, uint64_t val)
 185     {
 186         BaseDynInst<Impl>::setIntReg(si, idx, val);
 187     }
 188
 189     void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
 190     {
 191         BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
 192     }
 193
 194     void setFloatReg(const StaticInst *si, int idx, FloatReg val)
 195     {
 196         BaseDynInst<Impl>::setFloatReg(si, idx, val);
 197     }
 198
 199     void setFloatRegBits(const StaticInst *si, int idx,
 200             FloatRegBits val, int width)
 201     {
 202         BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
 203     }
 204
 205     void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
 206     {
 207         BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
 208     }
 209
 210     void setIntResult(uint64_t result) { this->instResult.integer = result; }
 211     void setDoubleResult(double result) { this->instResult.dbl = result; }
 212
 213     bool srcsReady();
 214     bool eaSrcsReady();
 215
 216     Fault execute();
 217
 218     Fault executeEAComp()
 219     { return NoFault; }
 220
 221     Fault executeMemAcc()
 222     { return this->staticInst->memAccInst()->execute(this, this->traceData); }
 223
 224     void clearDependents();
 225
 226     void clearMemDependents();
 227
 228   public:
 229     // ISA stuff
 230     MiscReg readMiscReg(int misc_reg);
 231
 232     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
 233
 234     Fault setMiscReg(int misc_reg, const MiscReg &val);
 235
 236     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
 237
 238 #if FULL_SYSTEM
 239     Fault hwrei();
 240     int readIntrFlag();
 241     void setIntrFlag(int val);
 242     bool inPalMode();
 243     void trap(Fault fault);
 244     bool simPalCheck(int palFunc);
 245 #else
 246     void syscall(uint64_t &callnum);
 247 #endif
 248
 249     ListIt iqIt;
 250     bool iqItValid;
 251 };
 252
 253 #endif // __CPU_OZONE_DYN_INST_HH__