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31 #ifndef __CPU_OZONE_DYN_INST_HH__
32 #define __CPU_OZONE_DYN_INST_HH__
34 #include "arch/isa_traits.hh"
35 #include "config/full_system.hh"
36 #include "cpu/base_dyn_inst.hh"
37 #include "cpu/inst_seq.hh"
38 #include "cpu/ozone/cpu.hh" // MUST include this
39 #include "cpu/ozone/ozone_impl.hh"
45 class OzoneDynInst : public BaseDynInst<Impl>
49 typedef typename Impl::OzoneCPU OzoneCPU;
51 typedef typename OzoneCPU::ImplState ImplState;
53 // Typedef for DynInstPtr. This is really just a RefCountingPtr<OoODynInst>.
54 typedef typename Impl::DynInstPtr DynInstPtr;
56 typedef TheISA::ExtMachInst ExtMachInst;
57 typedef TheISA::MachInst MachInst;
58 typedef TheISA::FloatReg FloatReg;
59 typedef TheISA::FloatRegBits FloatRegBits;
60 typedef TheISA::MiscReg MiscReg;
61 typedef typename std::list<DynInstPtr>::iterator ListIt;
63 // Note that this is duplicated from the BaseDynInst class; I'm
64 // simply not sure the enum would carry through so I could use it
65 // in array declarations in this class.
67 MaxInstSrcRegs = TheISA::MaxInstSrcRegs,
68 MaxInstDestRegs = TheISA::MaxInstDestRegs
71 OzoneDynInst(OzoneCPU *cpu);
73 OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
74 InstSeqNum seq_num, OzoneCPU *cpu);
76 OzoneDynInst(StaticInstPtr inst);
80 void setSrcInst(DynInstPtr &newSrcInst, int regIdx)
81 { srcInsts[regIdx] = newSrcInst; }
83 bool srcInstReady(int regIdx);
85 void setPrevDestInst(DynInstPtr &oldDestInst, int regIdx)
86 { prevDestInst[regIdx] = oldDestInst; }
88 DynInstPtr &getPrevDestInst(int regIdx)
89 { return prevDestInst[regIdx]; }
91 void addDependent(DynInstPtr &dependent_inst);
93 std::vector<DynInstPtr> &getDependents() { return dependents; }
94 std::vector<DynInstPtr> &getMemDeps() { return memDependents; }
95 std::list<DynInstPtr> &getMemSrcs() { return srcMemInsts; }
97 void wakeDependents();
99 void wakeMemDependents();
101 void addMemDependent(DynInstPtr &inst) { memDependents.push_back(inst); }
103 void addSrcMemInst(DynInstPtr &inst) { srcMemInsts.push_back(inst); }
105 void markMemInstReady(OzoneDynInst<Impl> *inst);
107 // For now I will remove instructions from the list when they wake
108 // up. In the future, you only really need a counter.
109 bool memDepReady() { return srcMemInsts.empty(); }
114 std::vector<DynInstPtr> dependents;
116 std::vector<DynInstPtr> memDependents;
118 std::list<DynInstPtr> srcMemInsts;
120 /** The instruction that produces the value of the source
121 * registers. These may be NULL if the value has already been
122 * read from the source instruction.
124 DynInstPtr srcInsts[MaxInstSrcRegs];
127 * Previous rename instruction for this destination.
129 DynInstPtr prevDestInst[MaxInstSrcRegs];
135 Fault completeAcc(Packet *pkt);
137 // The register accessor methods provide the index of the
138 // instruction's operand (e.g., 0 or 1), not the architectural
139 // register index, to simplify the implementation of register
140 // renaming. We find the architectural register index by indexing
141 // into the instruction's own operand index table. Note that a
142 // raw pointer to the StaticInst is provided instead of a
143 // ref-counted StaticInstPtr to redice overhead. This is fine as
144 // long as these methods don't copy the pointer into any long-term
145 // storage (which is pretty hard to imagine they would have reason
148 uint64_t readIntReg(const StaticInst *si, int idx)
150 return srcInsts[idx]->readIntResult();
153 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
157 return srcInsts[idx]->readFloatResult();
159 return srcInsts[idx]->readDoubleResult();
161 panic("Width not supported");
166 FloatReg readFloatReg(const StaticInst *si, int idx)
168 return srcInsts[idx]->readFloatResult();
171 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
173 return srcInsts[idx]->readIntResult();
176 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
178 return srcInsts[idx]->readIntResult();
181 /** @todo: Make results into arrays so they can handle multiple dest
184 void setIntReg(const StaticInst *si, int idx, uint64_t val)
186 BaseDynInst<Impl>::setIntReg(si, idx, val);
189 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
191 BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
194 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
196 BaseDynInst<Impl>::setFloatReg(si, idx, val);
199 void setFloatRegBits(const StaticInst *si, int idx,
200 FloatRegBits val, int width)
202 BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
205 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
207 BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
210 void setIntResult(uint64_t result) { this->instResult.integer = result; }
211 void setDoubleResult(double result) { this->instResult.dbl = result; }
218 Fault executeEAComp()
221 Fault executeMemAcc()
222 { return this->staticInst->memAccInst()->execute(this, this->traceData); }
224 void clearDependents();
226 void clearMemDependents();
230 MiscReg readMiscReg(int misc_reg);
232 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
234 Fault setMiscReg(int misc_reg, const MiscReg &val);
236 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
241 void setIntrFlag(int val);
243 void trap(Fault fault);
244 bool simPalCheck(int palFunc);
246 void syscall(uint64_t &callnum);
253 #endif // __CPU_OZONE_DYN_INST_HH__