src/cpu/ozone/dyn_inst.hh

   1 /*
   2  * Copyright (c) 2005-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_DYN_INST_HH__
  32 #define __CPU_OZONE_DYN_INST_HH__
  33
  34 #include "arch/isa_traits.hh"
  35 #include "arch/types.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/base_dyn_inst.hh"
  38 #include "cpu/inst_seq.hh"
  39 #include "cpu/ozone/cpu.hh"   // MUST include this
  40 #include "cpu/ozone/ozone_impl.hh"
  41
  42 #include <list>
  43 #include <vector>
  44
  45 template <class Impl>
  46 class OzoneDynInst : public BaseDynInst<Impl>
  47 {
  48   public:
  49     // Typedefs
  50     typedef typename Impl::OzoneCPU OzoneCPU;
  51
  52     typedef typename OzoneCPU::ImplState ImplState;
  53
  54     // Typedef for DynInstPtr.  This is really just a RefCountingPtr<OoODynInst>.
  55     typedef typename Impl::DynInstPtr DynInstPtr;
  56
  57     typedef TheISA::ExtMachInst ExtMachInst;
  58     typedef TheISA::MachInst MachInst;
  59     typedef TheISA::FloatReg FloatReg;
  60     typedef TheISA::FloatRegBits FloatRegBits;
  61     typedef TheISA::MiscReg MiscReg;
  62     typedef typename std::list<DynInstPtr>::iterator ListIt;
  63
  64     // Note that this is duplicated from the BaseDynInst class; I'm
  65     // simply not sure the enum would carry through so I could use it
  66     // in array declarations in this class.
  67     enum {
  68         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,
  69         MaxInstDestRegs = TheISA::MaxInstDestRegs
  70     };
  71
  72     OzoneDynInst(OzoneCPU *cpu);
  73
  74     OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
  75                  InstSeqNum seq_num, OzoneCPU *cpu);
  76
  77     OzoneDynInst(StaticInstPtr inst);
  78
  79     ~OzoneDynInst();
  80
  81     void setSrcInst(DynInstPtr &newSrcInst, int regIdx)
  82     { srcInsts[regIdx] = newSrcInst; }
  83
  84     bool srcInstReady(int regIdx);
  85
  86     void setPrevDestInst(DynInstPtr &oldDestInst, int regIdx)
  87     { prevDestInst[regIdx] = oldDestInst; }
  88
  89     DynInstPtr &getPrevDestInst(int regIdx)
  90     { return prevDestInst[regIdx]; }
  91
  92     void addDependent(DynInstPtr &dependent_inst);
  93
  94     std::vector<DynInstPtr> &getDependents() { return dependents; }
  95     std::vector<DynInstPtr> &getMemDeps() { return memDependents; }
  96     std::list<DynInstPtr> &getMemSrcs() { return srcMemInsts; }
  97
  98     void wakeDependents();
  99
 100     void wakeMemDependents();
 101
 102     void addMemDependent(DynInstPtr &inst) { memDependents.push_back(inst); }
 103
 104     void addSrcMemInst(DynInstPtr &inst) { srcMemInsts.push_back(inst); }
 105
 106     void markMemInstReady(OzoneDynInst<Impl> *inst);
 107
 108     // For now I will remove instructions from the list when they wake
 109     // up.  In the future, you only really need a counter.
 110     bool memDepReady() { return srcMemInsts.empty(); }
 111
 112   private:
 113     void initInstPtrs();
 114
 115     std::vector<DynInstPtr> dependents;
 116
 117     std::vector<DynInstPtr> memDependents;
 118
 119     std::list<DynInstPtr> srcMemInsts;
 120
 121     /** The instruction that produces the value of the source
 122      *  registers.  These may be NULL if the value has already been
 123      *  read from the source instruction.
 124      */
 125     DynInstPtr srcInsts[MaxInstSrcRegs];
 126
 127     /**
 128      *  Previous rename instruction for this destination.
 129      */
 130     DynInstPtr prevDestInst[MaxInstSrcRegs];
 131
 132   public:
 133
 134     Fault initiateAcc();
 135
 136     Fault completeAcc(Packet *pkt);
 137
 138     // The register accessor methods provide the index of the
 139     // instruction's operand (e.g., 0 or 1), not the architectural
 140     // register index, to simplify the implementation of register
 141     // renaming.  We find the architectural register index by indexing
 142     // into the instruction's own operand index table.  Note that a
 143     // raw pointer to the StaticInst is provided instead of a
 144     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 145     // long as these methods don't copy the pointer into any long-term
 146     // storage (which is pretty hard to imagine they would have reason
 147     // to do).
 148
 149     uint64_t readIntReg(const StaticInst *si, int idx)
 150     {
 151         return srcInsts[idx]->readIntResult();
 152     }
 153
 154     FloatReg readFloatReg(const StaticInst *si, int idx, int width)
 155     {
 156         switch(width) {
 157           case 32:
 158             return srcInsts[idx]->readFloatResult();
 159           case 64:
 160             return srcInsts[idx]->readDoubleResult();
 161           default:
 162             panic("Width not supported");
 163             return 0;
 164         }
 165     }
 166
 167     FloatReg readFloatReg(const StaticInst *si, int idx)
 168     {
 169         return srcInsts[idx]->readFloatResult();
 170     }
 171
 172     FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
 173     {
 174         return srcInsts[idx]->readIntResult();
 175     }
 176
 177     FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
 178     {
 179         return srcInsts[idx]->readIntResult();
 180     }
 181
 182     /** @todo: Make results into arrays so they can handle multiple dest
 183      *  registers.
 184      */
 185     void setIntReg(const StaticInst *si, int idx, uint64_t val)
 186     {
 187         BaseDynInst<Impl>::setIntReg(si, idx, val);
 188     }
 189
 190     void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
 191     {
 192         BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
 193     }
 194
 195     void setFloatReg(const StaticInst *si, int idx, FloatReg val)
 196     {
 197         BaseDynInst<Impl>::setFloatReg(si, idx, val);
 198     }
 199
 200     void setFloatRegBits(const StaticInst *si, int idx,
 201             FloatRegBits val, int width)
 202     {
 203         BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
 204     }
 205
 206     void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
 207     {
 208         BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
 209     }
 210
 211     void setIntResult(uint64_t result) { this->instResult.integer = result; }
 212     void setDoubleResult(double result) { this->instResult.dbl = result; }
 213
 214     bool srcsReady();
 215     bool eaSrcsReady();
 216
 217     Fault execute();
 218
 219     Fault executeEAComp()
 220     { return NoFault; }
 221
 222     Fault executeMemAcc()
 223     { return this->staticInst->memAccInst()->execute(this, this->traceData); }
 224
 225     void clearDependents();
 226
 227     void clearMemDependents();
 228
 229   public:
 230     // ISA stuff
 231     MiscReg readMiscReg(int misc_reg);
 232
 233     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
 234
 235     Fault setMiscReg(int misc_reg, const MiscReg &val);
 236
 237     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
 238
 239 #if FULL_SYSTEM
 240     Fault hwrei();
 241     int readIntrFlag();
 242     void setIntrFlag(int val);
 243     bool inPalMode();
 244     void trap(Fault fault);
 245     bool simPalCheck(int palFunc);
 246 #else
 247     void syscall(uint64_t &callnum);
 248 #endif
 249
 250     ListIt iqIt;
 251     bool iqItValid;
 252 };
 253
 254 #endif // __CPU_OZONE_DYN_INST_HH__