src/cpu/ozone/dyn_inst.hh

   1 /*
   2  * Copyright (c) 2005-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_DYN_INST_HH__
  32 #define __CPU_OZONE_DYN_INST_HH__
  33
  34 #include "arch/isa_traits.hh"
  35 #include "arch/types.hh"
  36 #include "config/full_system.hh"
  37 #include "config/the_isa.hh"
  38 #include "cpu/base_dyn_inst.hh"
  39 #include "cpu/inst_seq.hh"
  40 #include "cpu/ozone/cpu.hh"   // MUST include this
  41 #include "cpu/ozone/ozone_impl.hh"
  42
  43 #include <list>
  44 #include <vector>
  45
  46 template <class Impl>
  47 class OzoneDynInst : public BaseDynInst<Impl>
  48 {
  49   public:
  50     // Typedefs
  51     typedef typename Impl::OzoneCPU OzoneCPU;
  52
  53     typedef typename OzoneCPU::ImplState ImplState;
  54
  55     // Typedef for DynInstPtr.  This is really just a RefCountingPtr<OoODynInst>.
  56     typedef typename Impl::DynInstPtr DynInstPtr;
  57
  58     typedef TheISA::ExtMachInst ExtMachInst;
  59     typedef TheISA::MachInst MachInst;
  60     typedef TheISA::FloatReg FloatReg;
  61     typedef TheISA::FloatRegBits FloatRegBits;
  62     typedef TheISA::MiscReg MiscReg;
  63     typedef typename std::list<DynInstPtr>::iterator ListIt;
  64
  65     // Note that this is duplicated from the BaseDynInst class; I'm
  66     // simply not sure the enum would carry through so I could use it
  67     // in array declarations in this class.
  68     enum {
  69         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,
  70         MaxInstDestRegs = TheISA::MaxInstDestRegs
  71     };
  72
  73     OzoneDynInst(OzoneCPU *cpu);
  74
  75     OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
  76                  InstSeqNum seq_num, OzoneCPU *cpu);
  77
  78     OzoneDynInst(StaticInstPtr inst);
  79
  80     ~OzoneDynInst();
  81
  82     void setSrcInst(DynInstPtr &newSrcInst, int regIdx)
  83     { srcInsts[regIdx] = newSrcInst; }
  84
  85     bool srcInstReady(int regIdx);
  86
  87     void setPrevDestInst(DynInstPtr &oldDestInst, int regIdx)
  88     { prevDestInst[regIdx] = oldDestInst; }
  89
  90     DynInstPtr &getPrevDestInst(int regIdx)
  91     { return prevDestInst[regIdx]; }
  92
  93     void addDependent(DynInstPtr &dependent_inst);
  94
  95     std::vector<DynInstPtr> &getDependents() { return dependents; }
  96     std::vector<DynInstPtr> &getMemDeps() { return memDependents; }
  97     std::list<DynInstPtr> &getMemSrcs() { return srcMemInsts; }
  98
  99     void wakeDependents();
 100
 101     void wakeMemDependents();
 102
 103     void addMemDependent(DynInstPtr &inst) { memDependents.push_back(inst); }
 104
 105     void addSrcMemInst(DynInstPtr &inst) { srcMemInsts.push_back(inst); }
 106
 107     void markMemInstReady(OzoneDynInst<Impl> *inst);
 108
 109     // For now I will remove instructions from the list when they wake
 110     // up.  In the future, you only really need a counter.
 111     bool memDepReady() { return srcMemInsts.empty(); }
 112
 113   private:
 114     void initInstPtrs();
 115
 116     std::vector<DynInstPtr> dependents;
 117
 118     std::vector<DynInstPtr> memDependents;
 119
 120     std::list<DynInstPtr> srcMemInsts;
 121
 122     /** The instruction that produces the value of the source
 123      *  registers.  These may be NULL if the value has already been
 124      *  read from the source instruction.
 125      */
 126     DynInstPtr srcInsts[MaxInstSrcRegs];
 127
 128     /**
 129      *  Previous rename instruction for this destination.
 130      */
 131     DynInstPtr prevDestInst[MaxInstSrcRegs];
 132
 133   public:
 134
 135     Fault initiateAcc();
 136
 137     Fault completeAcc(PacketPtr pkt);
 138
 139     // The register accessor methods provide the index of the
 140     // instruction's operand (e.g., 0 or 1), not the architectural
 141     // register index, to simplify the implementation of register
 142     // renaming.  We find the architectural register index by indexing
 143     // into the instruction's own operand index table.  Note that a
 144     // raw pointer to the StaticInst is provided instead of a
 145     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 146     // long as these methods don't copy the pointer into any long-term
 147     // storage (which is pretty hard to imagine they would have reason
 148     // to do).
 149
 150     uint64_t readIntRegOperand(const StaticInst *si, int idx)
 151     {
 152         return srcInsts[idx]->readIntResult();
 153     }
 154
 155     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
 156     {
 157         return srcInsts[idx]->readFloatResult();
 158     }
 159
 160     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
 161     {
 162         return srcInsts[idx]->readFloatResult();
 163     }
 164
 165     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
 166     {
 167         return srcInsts[idx]->readIntResult();
 168     }
 169
 170     /** @todo: Make results into arrays so they can handle multiple dest
 171      *  registers.
 172      */
 173     void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
 174     {
 175         BaseDynInst<Impl>::setIntReg(si, idx, val);
 176     }
 177
 178     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
 179     {
 180         BaseDynInst<Impl>::setFloatReg(si, idx, val);
 181     }
 182
 183     void setFloatRegOperandBits(const StaticInst *si, int idx,
 184                                 FloatRegBits val)
 185     {
 186         BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
 187     }
 188
 189     void setIntResult(uint64_t result) { this->instResult.integer = result; }
 190     void setDoubleResult(double result) { this->instResult.dbl = result; }
 191
 192     bool srcsReady();
 193     bool eaSrcsReady();
 194
 195     Fault execute();
 196
 197     Fault executeEAComp()
 198     { return NoFault; }
 199
 200     Fault executeMemAcc()
 201     { return this->staticInst->memAccInst()->execute(this, this->traceData); }
 202
 203     void clearDependents();
 204
 205     void clearMemDependents();
 206
 207   public:
 208     // ISA stuff
 209     MiscReg readMiscRegNoEffect(int misc_reg);
 210
 211     MiscReg readMiscReg(int misc_reg);
 212
 213     void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
 214
 215     void setMiscReg(int misc_reg, const MiscReg &val);
 216
 217 #if FULL_SYSTEM
 218     Fault hwrei();
 219     void trap(Fault fault);
 220     bool simPalCheck(int palFunc);
 221 #else
 222     void syscall(uint64_t &callnum);
 223 #endif
 224
 225     ListIt iqIt;
 226     bool iqItValid;
 227 };
 228
 229 #endif // __CPU_OZONE_DYN_INST_HH__