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31 #ifndef __CPU_OZONE_DYN_INST_HH__
32 #define __CPU_OZONE_DYN_INST_HH__
34 #include "arch/isa_traits.hh"
35 #include "config/full_system.hh"
36 #include "cpu/base_dyn_inst.hh"
37 #include "cpu/ozone/cpu.hh" // MUST include this
38 #include "cpu/inst_seq.hh"
39 //#include "cpu/ozone/simple_impl.hh" // Would be nice to not have to include this
40 #include "cpu/ozone/ozone_impl.hh"
46 class OzoneDynInst : public BaseDynInst<Impl>
50 typedef typename Impl::FullCPU FullCPU;
52 typedef typename FullCPU::ImplState ImplState;
54 // Typedef for DynInstPtr. This is really just a RefCountingPtr<OoODynInst>.
55 typedef typename Impl::DynInstPtr DynInstPtr;
57 typedef TheISA::ExtMachInst ExtMachInst;
58 typedef TheISA::MachInst MachInst;
59 typedef TheISA::MiscReg MiscReg;
60 typedef typename std::list<DynInstPtr>::iterator ListIt;
62 // Note that this is duplicated from the BaseDynInst class; I'm
63 // simply not sure the enum would carry through so I could use it
64 // in array declarations in this class.
66 MaxInstSrcRegs = TheISA::MaxInstSrcRegs,
67 MaxInstDestRegs = TheISA::MaxInstDestRegs
70 OzoneDynInst(FullCPU *cpu);
72 OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
73 InstSeqNum seq_num, FullCPU *cpu);
75 OzoneDynInst(StaticInstPtr inst);
79 void setSrcInst(DynInstPtr &newSrcInst, int regIdx)
80 { srcInsts[regIdx] = newSrcInst; }
82 bool srcInstReady(int regIdx);
84 void setPrevDestInst(DynInstPtr &oldDestInst, int regIdx)
85 { prevDestInst[regIdx] = oldDestInst; }
87 DynInstPtr &getPrevDestInst(int regIdx)
88 { return prevDestInst[regIdx]; }
90 void addDependent(DynInstPtr &dependent_inst);
92 std::vector<DynInstPtr> &getDependents() { return dependents; }
93 std::vector<DynInstPtr> &getMemDeps() { return memDependents; }
94 std::list<DynInstPtr> &getMemSrcs() { return srcMemInsts; }
96 void wakeDependents();
98 void wakeMemDependents();
100 void addMemDependent(DynInstPtr &inst) { memDependents.push_back(inst); }
102 void addSrcMemInst(DynInstPtr &inst) { srcMemInsts.push_back(inst); }
104 void markMemInstReady(OzoneDynInst<Impl> *inst);
106 // For now I will remove instructions from the list when they wake
107 // up. In the future, you only really need a counter.
108 bool memDepReady() { return srcMemInsts.empty(); }
113 std::vector<DynInstPtr> dependents;
115 std::vector<DynInstPtr> memDependents;
117 std::list<DynInstPtr> srcMemInsts;
119 /** The instruction that produces the value of the source
120 * registers. These may be NULL if the value has already been
121 * read from the source instruction.
123 DynInstPtr srcInsts[MaxInstSrcRegs];
126 * Previous rename instruction for this destination.
128 DynInstPtr prevDestInst[MaxInstSrcRegs];
136 // The register accessor methods provide the index of the
137 // instruction's operand (e.g., 0 or 1), not the architectural
138 // register index, to simplify the implementation of register
139 // renaming. We find the architectural register index by indexing
140 // into the instruction's own operand index table. Note that a
141 // raw pointer to the StaticInst is provided instead of a
142 // ref-counted StaticInstPtr to redice overhead. This is fine as
143 // long as these methods don't copy the pointer into any long-term
144 // storage (which is pretty hard to imagine they would have reason
147 uint64_t readIntReg(const StaticInst *si, int idx)
149 return srcInsts[idx]->readIntResult();
152 float readFloatRegSingle(const StaticInst *si, int idx)
154 return srcInsts[idx]->readFloatResult();
157 double readFloatRegDouble(const StaticInst *si, int idx)
159 return srcInsts[idx]->readDoubleResult();
162 uint64_t readFloatRegInt(const StaticInst *si, int idx)
164 return srcInsts[idx]->readIntResult();
167 /** @todo: Make results into arrays so they can handle multiple dest
170 void setIntReg(const StaticInst *si, int idx, uint64_t val)
172 BaseDynInst<Impl>::setIntReg(si, idx, val);
175 void setFloatRegSingle(const StaticInst *si, int idx, float val)
177 BaseDynInst<Impl>::setFloatRegSingle(si, idx, val);
180 void setFloatRegDouble(const StaticInst *si, int idx, double val)
182 BaseDynInst<Impl>::setFloatRegDouble(si, idx, val);
185 void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
187 BaseDynInst<Impl>::setFloatRegInt(si, idx, val);
190 void setIntResult(uint64_t result) { this->instResult.integer = result; }
191 void setDoubleResult(double result) { this->instResult.dbl = result; }
198 Fault executeEAComp()
201 Fault executeMemAcc()
202 { return this->staticInst->memAccInst()->execute(this, this->traceData); }
204 void clearDependents();
206 void clearMemDependents();
210 MiscReg readMiscReg(int misc_reg);
212 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault);
214 Fault setMiscReg(int misc_reg, const MiscReg &val);
216 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val);
221 void setIntrFlag(int val);
223 void trap(Fault fault);
224 bool simPalCheck(int palFunc);
233 #endif // __CPU_OZONE_DYN_INST_HH__