src/cpu/ozone/dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2005-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "config/the_isa.hh"
  32 #include "cpu/ozone/dyn_inst.hh"
  33 #include "kern/kernel_stats.hh"
  34 #include "sim/faults.hh"
  35
  36 template <class Impl>
  37 OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
  38     : BaseDynInst<Impl>(0, 0, 0, 0, cpu)
  39 {
  40     this->setResultReady();
  41
  42     initInstPtrs();
  43 }
  44
  45 template <class Impl>
  46 OzoneDynInst<Impl>::OzoneDynInst(StaticInstPtr _staticInst)
  47     : BaseDynInst<Impl>(_staticInst)
  48 {
  49     initInstPtrs();
  50 }
  51
  52 template <class Impl>
  53 OzoneDynInst<Impl>::~OzoneDynInst()
  54 {
  55     DPRINTF(BE, "[sn:%lli] destructor called\n", this->seqNum);
  56     for (int i = 0; i < this->numSrcRegs(); ++i) {
  57         srcInsts[i] = NULL;
  58     }
  59
  60     for (int i = 0; i < this->numDestRegs(); ++i) {
  61         prevDestInst[i] = NULL;
  62     }
  63
  64     dependents.clear();
  65 }
  66
  67 template <class Impl>
  68 Fault
  69 OzoneDynInst<Impl>::execute()
  70 {
  71     // @todo: Pretty convoluted way to avoid squashing from happening when using
  72     // the XC during an instruction's execution (specifically for instructions
  73     // that have sideeffects that use the XC).  Fix this.
  74     bool in_syscall = this->thread->inSyscall;
  75     this->thread->inSyscall = true;
  76
  77     this->fault = this->staticInst->execute(this, this->traceData);
  78
  79     this->thread->inSyscall = in_syscall;
  80
  81     return this->fault;
  82 }
  83
  84 template <class Impl>
  85 Fault
  86 OzoneDynInst<Impl>::initiateAcc()
  87 {
  88     // @todo: Pretty convoluted way to avoid squashing from happening when using
  89     // the XC during an instruction's execution (specifically for instructions
  90     // that have sideeffects that use the XC).  Fix this.
  91     bool in_syscall = this->thread->inSyscall;
  92     this->thread->inSyscall = true;
  93
  94     this->fault = this->staticInst->initiateAcc(this, this->traceData);
  95
  96     this->thread->inSyscall = in_syscall;
  97
  98     return this->fault;
  99 }
 100
 101 template <class Impl>
 102 Fault
 103 OzoneDynInst<Impl>::completeAcc(PacketPtr pkt)
 104 {
 105     this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
 106
 107     return this->fault;
 108 }
 109
 110 template <class Impl>
 111 bool
 112 OzoneDynInst<Impl>::srcInstReady(int regIdx)
 113 {
 114     return srcInsts[regIdx]->isResultReady();
 115 }
 116
 117 template <class Impl>
 118 void
 119 OzoneDynInst<Impl>::addDependent(DynInstPtr &dependent_inst)
 120 {
 121     dependents.push_back(dependent_inst);
 122 }
 123
 124 template <class Impl>
 125 void
 126 OzoneDynInst<Impl>::wakeDependents()
 127 {
 128     for (int i = 0; i < dependents.size(); ++i) {
 129         dependents[i]->markSrcRegReady();
 130     }
 131 }
 132
 133 template <class Impl>
 134 void
 135 OzoneDynInst<Impl>::wakeMemDependents()
 136 {
 137     for (int i = 0; i < memDependents.size(); ++i) {
 138         memDependents[i]->markMemInstReady(this);
 139     }
 140 }
 141
 142 template <class Impl>
 143 void
 144 OzoneDynInst<Impl>::markMemInstReady(OzoneDynInst<Impl> *inst)
 145 {
 146     ListIt mem_it = srcMemInsts.begin();
 147     while ((*mem_it) != inst && mem_it != srcMemInsts.end()) {
 148         mem_it++;
 149     }
 150     assert(mem_it != srcMemInsts.end());
 151
 152     srcMemInsts.erase(mem_it);
 153 }
 154
 155 template <class Impl>
 156 void
 157 OzoneDynInst<Impl>::initInstPtrs()
 158 {
 159     for (int i = 0; i < MaxInstSrcRegs; ++i) {
 160         srcInsts[i] = NULL;
 161     }
 162     iqItValid = false;
 163 }
 164
 165 template <class Impl>
 166 bool
 167 OzoneDynInst<Impl>::srcsReady()
 168 {
 169     for (int i = 0; i < this->numSrcRegs(); ++i) {
 170         if (!srcInsts[i]->isResultReady())
 171             return false;
 172     }
 173
 174     return true;
 175 }
 176
 177 template <class Impl>
 178 bool
 179 OzoneDynInst<Impl>::eaSrcsReady()
 180 {
 181     for (int i = 1; i < this->numSrcRegs(); ++i) {
 182         if (!srcInsts[i]->isResultReady())
 183             return false;
 184     }
 185
 186     return true;
 187 }
 188
 189 template <class Impl>
 190 void
 191 OzoneDynInst<Impl>::clearDependents()
 192 {
 193     dependents.clear();
 194     for (int i = 0; i < this->numSrcRegs(); ++i) {
 195         srcInsts[i] = NULL;
 196     }
 197     for (int i = 0; i < this->numDestRegs(); ++i) {
 198         prevDestInst[i] = NULL;
 199     }
 200 }
 201
 202 template <class Impl>
 203 void
 204 OzoneDynInst<Impl>::clearMemDependents()
 205 {
 206     memDependents.clear();
 207 }
 208
 209 template <class Impl>
 210 TheISA::MiscReg
 211 OzoneDynInst<Impl>::readMiscRegNoEffect(int misc_reg)
 212 {
 213     return this->thread->readMiscRegNoEffect(misc_reg);
 214 }
 215
 216 template <class Impl>
 217 TheISA::MiscReg
 218 OzoneDynInst<Impl>::readMiscReg(int misc_reg)
 219 {
 220     return this->thread->readMiscReg(misc_reg);
 221 }
 222
 223 template <class Impl>
 224 void
 225 OzoneDynInst<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 226 {
 227     this->setIntResult(val);
 228     this->thread->setMiscRegNoEffect(misc_reg, val);
 229 }
 230
 231 template <class Impl>
 232 void
 233 OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
 234 {
 235     this->thread->setMiscReg(misc_reg, val);
 236 }
 237
 238 template <class Impl>
 239 Fault
 240 OzoneDynInst<Impl>::hwrei()
 241 {
 242     if (!(this->readPC() & 0x3))
 243         return new AlphaISA::UnimplementedOpcodeFault;
 244
 245     this->setNextPC(this->thread->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
 246
 247     this->cpu->hwrei();
 248
 249     // FIXME: XXX check for interrupts? XXX
 250     return NoFault;
 251 }
 252
 253 template <class Impl>
 254 void
 255 OzoneDynInst<Impl>::trap(Fault fault)
 256 {
 257     fault->invoke(this->thread->getTC());
 258 }
 259
 260 template <class Impl>
 261 bool
 262 OzoneDynInst<Impl>::simPalCheck(int palFunc)
 263 {
 264     return this->cpu->simPalCheck(palFunc);
 265 }
 266
 267 template <class Impl>
 268 void
 269 OzoneDynInst<Impl>::syscall(uint64_t &callnum)
 270 {
 271     this->cpu->syscall(callnum);
 272 }