2 * Copyright (c) 2005-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "config/the_isa.hh"
32 #include "cpu/ozone/dyn_inst.hh"
33 #include "kern/kernel_stats.hh"
34 #include "sim/faults.hh"
37 OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
38 : BaseDynInst<Impl>(0, 0, 0, 0, cpu)
40 this->setResultReady();
46 OzoneDynInst<Impl>::OzoneDynInst(StaticInstPtr _staticInst)
47 : BaseDynInst<Impl>(_staticInst)
53 OzoneDynInst<Impl>::~OzoneDynInst()
55 DPRINTF(BE, "[sn:%lli] destructor called\n", this->seqNum);
56 for (int i = 0; i < this->numSrcRegs(); ++i) {
60 for (int i = 0; i < this->numDestRegs(); ++i) {
61 prevDestInst[i] = NULL;
69 OzoneDynInst<Impl>::execute()
71 // @todo: Pretty convoluted way to avoid squashing from happening when using
72 // the XC during an instruction's execution (specifically for instructions
73 // that have sideeffects that use the XC). Fix this.
74 bool in_syscall = this->thread->inSyscall;
75 this->thread->inSyscall = true;
77 this->fault = this->staticInst->execute(this, this->traceData);
79 this->thread->inSyscall = in_syscall;
86 OzoneDynInst<Impl>::initiateAcc()
88 // @todo: Pretty convoluted way to avoid squashing from happening when using
89 // the XC during an instruction's execution (specifically for instructions
90 // that have sideeffects that use the XC). Fix this.
91 bool in_syscall = this->thread->inSyscall;
92 this->thread->inSyscall = true;
94 this->fault = this->staticInst->initiateAcc(this, this->traceData);
96 this->thread->inSyscall = in_syscall;
101 template <class Impl>
103 OzoneDynInst<Impl>::completeAcc(PacketPtr pkt)
105 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
110 template <class Impl>
112 OzoneDynInst<Impl>::srcInstReady(int regIdx)
114 return srcInsts[regIdx]->isResultReady();
117 template <class Impl>
119 OzoneDynInst<Impl>::addDependent(DynInstPtr &dependent_inst)
121 dependents.push_back(dependent_inst);
124 template <class Impl>
126 OzoneDynInst<Impl>::wakeDependents()
128 for (int i = 0; i < dependents.size(); ++i) {
129 dependents[i]->markSrcRegReady();
133 template <class Impl>
135 OzoneDynInst<Impl>::wakeMemDependents()
137 for (int i = 0; i < memDependents.size(); ++i) {
138 memDependents[i]->markMemInstReady(this);
142 template <class Impl>
144 OzoneDynInst<Impl>::markMemInstReady(OzoneDynInst<Impl> *inst)
146 ListIt mem_it = srcMemInsts.begin();
147 while ((*mem_it) != inst && mem_it != srcMemInsts.end()) {
150 assert(mem_it != srcMemInsts.end());
152 srcMemInsts.erase(mem_it);
155 template <class Impl>
157 OzoneDynInst<Impl>::initInstPtrs()
159 for (int i = 0; i < MaxInstSrcRegs; ++i) {
165 template <class Impl>
167 OzoneDynInst<Impl>::srcsReady()
169 for (int i = 0; i < this->numSrcRegs(); ++i) {
170 if (!srcInsts[i]->isResultReady())
177 template <class Impl>
179 OzoneDynInst<Impl>::eaSrcsReady()
181 for (int i = 1; i < this->numSrcRegs(); ++i) {
182 if (!srcInsts[i]->isResultReady())
189 template <class Impl>
191 OzoneDynInst<Impl>::clearDependents()
194 for (int i = 0; i < this->numSrcRegs(); ++i) {
197 for (int i = 0; i < this->numDestRegs(); ++i) {
198 prevDestInst[i] = NULL;
202 template <class Impl>
204 OzoneDynInst<Impl>::clearMemDependents()
206 memDependents.clear();
209 template <class Impl>
211 OzoneDynInst<Impl>::readMiscRegNoEffect(int misc_reg)
213 return this->thread->readMiscRegNoEffect(misc_reg);
216 template <class Impl>
218 OzoneDynInst<Impl>::readMiscReg(int misc_reg)
220 return this->thread->readMiscReg(misc_reg);
223 template <class Impl>
225 OzoneDynInst<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
227 this->setIntResult(val);
228 this->thread->setMiscRegNoEffect(misc_reg, val);
231 template <class Impl>
233 OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
235 this->thread->setMiscReg(misc_reg, val);
238 template <class Impl>
240 OzoneDynInst<Impl>::hwrei()
242 if (!(this->readPC() & 0x3))
243 return new AlphaISA::UnimplementedOpcodeFault;
245 this->setNextPC(this->thread->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR));
249 // FIXME: XXX check for interrupts? XXX
253 template <class Impl>
255 OzoneDynInst<Impl>::trap(Fault fault)
257 fault->invoke(this->thread->getTC());
260 template <class Impl>
262 OzoneDynInst<Impl>::simPalCheck(int palFunc)
264 return this->cpu->simPalCheck(palFunc);
267 template <class Impl>
269 OzoneDynInst<Impl>::syscall(uint64_t &callnum)
271 this->cpu->syscall(callnum);