Cleaned up include files and got rid of many using directives in header files.
[gem5.git] / src / cpu / ozone / dyn_inst_impl.hh
1 /*
2 * Copyright (c) 2005-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31 #include "arch/faults.hh"
32 #include "config/full_system.hh"
33 #include "cpu/ozone/dyn_inst.hh"
34 #include "kern/kernel_stats.hh"
35
36 template <class Impl>
37 OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
38 : BaseDynInst<Impl>(0, 0, 0, 0, cpu)
39 {
40 this->setResultReady();
41
42 initInstPtrs();
43 }
44
45 template <class Impl>
46 OzoneDynInst<Impl>::OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
47 InstSeqNum seq_num, OzoneCPU *cpu)
48 : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
49 {
50 initInstPtrs();
51 }
52
53 template <class Impl>
54 OzoneDynInst<Impl>::OzoneDynInst(StaticInstPtr _staticInst)
55 : BaseDynInst<Impl>(_staticInst)
56 {
57 initInstPtrs();
58 }
59
60 template <class Impl>
61 OzoneDynInst<Impl>::~OzoneDynInst()
62 {
63 DPRINTF(BE, "[sn:%lli] destructor called\n", this->seqNum);
64 for (int i = 0; i < this->numSrcRegs(); ++i) {
65 srcInsts[i] = NULL;
66 }
67
68 for (int i = 0; i < this->numDestRegs(); ++i) {
69 prevDestInst[i] = NULL;
70 }
71
72 dependents.clear();
73 }
74
75 template <class Impl>
76 Fault
77 OzoneDynInst<Impl>::execute()
78 {
79 // @todo: Pretty convoluted way to avoid squashing from happening when using
80 // the XC during an instruction's execution (specifically for instructions
81 // that have sideeffects that use the XC). Fix this.
82 bool in_syscall = this->thread->inSyscall;
83 this->thread->inSyscall = true;
84
85 this->fault = this->staticInst->execute(this, this->traceData);
86
87 this->thread->inSyscall = in_syscall;
88
89 return this->fault;
90 }
91
92 template <class Impl>
93 Fault
94 OzoneDynInst<Impl>::initiateAcc()
95 {
96 // @todo: Pretty convoluted way to avoid squashing from happening when using
97 // the XC during an instruction's execution (specifically for instructions
98 // that have sideeffects that use the XC). Fix this.
99 bool in_syscall = this->thread->inSyscall;
100 this->thread->inSyscall = true;
101
102 this->fault = this->staticInst->initiateAcc(this, this->traceData);
103
104 this->thread->inSyscall = in_syscall;
105
106 return this->fault;
107 }
108
109 template <class Impl>
110 Fault
111 OzoneDynInst<Impl>::completeAcc(Packet *pkt)
112 {
113 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
114
115 return this->fault;
116 }
117
118 template <class Impl>
119 bool
120 OzoneDynInst<Impl>::srcInstReady(int regIdx)
121 {
122 return srcInsts[regIdx]->isResultReady();
123 }
124
125 template <class Impl>
126 void
127 OzoneDynInst<Impl>::addDependent(DynInstPtr &dependent_inst)
128 {
129 dependents.push_back(dependent_inst);
130 }
131
132 template <class Impl>
133 void
134 OzoneDynInst<Impl>::wakeDependents()
135 {
136 for (int i = 0; i < dependents.size(); ++i) {
137 dependents[i]->markSrcRegReady();
138 }
139 }
140
141 template <class Impl>
142 void
143 OzoneDynInst<Impl>::wakeMemDependents()
144 {
145 for (int i = 0; i < memDependents.size(); ++i) {
146 memDependents[i]->markMemInstReady(this);
147 }
148 }
149
150 template <class Impl>
151 void
152 OzoneDynInst<Impl>::markMemInstReady(OzoneDynInst<Impl> *inst)
153 {
154 ListIt mem_it = srcMemInsts.begin();
155 while ((*mem_it) != inst && mem_it != srcMemInsts.end()) {
156 mem_it++;
157 }
158 assert(mem_it != srcMemInsts.end());
159
160 srcMemInsts.erase(mem_it);
161 }
162
163 template <class Impl>
164 void
165 OzoneDynInst<Impl>::initInstPtrs()
166 {
167 for (int i = 0; i < MaxInstSrcRegs; ++i) {
168 srcInsts[i] = NULL;
169 }
170 iqItValid = false;
171 }
172
173 template <class Impl>
174 bool
175 OzoneDynInst<Impl>::srcsReady()
176 {
177 for (int i = 0; i < this->numSrcRegs(); ++i) {
178 if (!srcInsts[i]->isResultReady())
179 return false;
180 }
181
182 return true;
183 }
184
185 template <class Impl>
186 bool
187 OzoneDynInst<Impl>::eaSrcsReady()
188 {
189 for (int i = 1; i < this->numSrcRegs(); ++i) {
190 if (!srcInsts[i]->isResultReady())
191 return false;
192 }
193
194 return true;
195 }
196
197 template <class Impl>
198 void
199 OzoneDynInst<Impl>::clearDependents()
200 {
201 dependents.clear();
202 for (int i = 0; i < this->numSrcRegs(); ++i) {
203 srcInsts[i] = NULL;
204 }
205 for (int i = 0; i < this->numDestRegs(); ++i) {
206 prevDestInst[i] = NULL;
207 }
208 }
209
210 template <class Impl>
211 void
212 OzoneDynInst<Impl>::clearMemDependents()
213 {
214 memDependents.clear();
215 }
216
217 template <class Impl>
218 MiscReg
219 OzoneDynInst<Impl>::readMiscReg(int misc_reg)
220 {
221 return this->thread->readMiscReg(misc_reg);
222 }
223
224 template <class Impl>
225 MiscReg
226 OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault)
227 {
228 return this->thread->readMiscRegWithEffect(misc_reg, fault);
229 }
230
231 template <class Impl>
232 Fault
233 OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
234 {
235 this->setIntResult(val);
236 return this->thread->setMiscReg(misc_reg, val);
237 }
238
239 template <class Impl>
240 Fault
241 OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
242 {
243 return this->thread->setMiscRegWithEffect(misc_reg, val);
244 }
245
246 #if FULL_SYSTEM
247
248 template <class Impl>
249 Fault
250 OzoneDynInst<Impl>::hwrei()
251 {
252 if (!this->cpu->inPalMode(this->readPC()))
253 return new AlphaISA::UnimplementedOpcodeFault;
254
255 this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
256
257 this->cpu->hwrei();
258
259 // FIXME: XXX check for interrupts? XXX
260 return NoFault;
261 }
262
263 template <class Impl>
264 int
265 OzoneDynInst<Impl>::readIntrFlag()
266 {
267 return this->cpu->readIntrFlag();
268 }
269
270 template <class Impl>
271 void
272 OzoneDynInst<Impl>::setIntrFlag(int val)
273 {
274 this->cpu->setIntrFlag(val);
275 }
276
277 template <class Impl>
278 bool
279 OzoneDynInst<Impl>::inPalMode()
280 {
281 return this->cpu->inPalMode();
282 }
283
284 template <class Impl>
285 void
286 OzoneDynInst<Impl>::trap(Fault fault)
287 {
288 fault->invoke(this->thread->getTC());
289 }
290
291 template <class Impl>
292 bool
293 OzoneDynInst<Impl>::simPalCheck(int palFunc)
294 {
295 return this->cpu->simPalCheck(palFunc);
296 }
297 #else
298 template <class Impl>
299 void
300 OzoneDynInst<Impl>::syscall(uint64_t &callnum)
301 {
302 this->cpu->syscall(callnum);
303 }
304 #endif