Merge m5.eecs.umich.edu:/bk/newmem
[gem5.git] / src / cpu / ozone / dyn_inst_impl.hh
1 /*
2 * Copyright (c) 2005-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31 #include "arch/faults.hh"
32 #include "arch/isa_traits.hh"
33 #include "config/full_system.hh"
34 #include "cpu/ozone/dyn_inst.hh"
35 #include "kern/kernel_stats.hh"
36
37 using namespace TheISA;
38
39 template <class Impl>
40 OzoneDynInst<Impl>::OzoneDynInst(FullCPU *cpu)
41 : BaseDynInst<Impl>(0, 0, 0, 0, cpu)
42 {
43 this->setResultReady();
44
45 initInstPtrs();
46 }
47
48 template <class Impl>
49 OzoneDynInst<Impl>::OzoneDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
50 InstSeqNum seq_num, FullCPU *cpu)
51 : BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
52 {
53 initInstPtrs();
54 }
55
56 template <class Impl>
57 OzoneDynInst<Impl>::OzoneDynInst(StaticInstPtr _staticInst)
58 : BaseDynInst<Impl>(_staticInst)
59 {
60 initInstPtrs();
61 }
62
63 template <class Impl>
64 OzoneDynInst<Impl>::~OzoneDynInst()
65 {
66 DPRINTF(BE, "[sn:%lli] destructor called\n", this->seqNum);
67 for (int i = 0; i < this->numSrcRegs(); ++i) {
68 srcInsts[i] = NULL;
69 }
70
71 for (int i = 0; i < this->numDestRegs(); ++i) {
72 prevDestInst[i] = NULL;
73 }
74
75 dependents.clear();
76 }
77
78 template <class Impl>
79 Fault
80 OzoneDynInst<Impl>::execute()
81 {
82 // @todo: Pretty convoluted way to avoid squashing from happening when using
83 // the XC during an instruction's execution (specifically for instructions
84 // that have sideeffects that use the XC). Fix this.
85 bool in_syscall = this->thread->inSyscall;
86 this->thread->inSyscall = true;
87
88 this->fault = this->staticInst->execute(this, this->traceData);
89
90 this->thread->inSyscall = in_syscall;
91
92 return this->fault;
93 }
94
95 template <class Impl>
96 Fault
97 OzoneDynInst<Impl>::initiateAcc()
98 {
99 // @todo: Pretty convoluted way to avoid squashing from happening when using
100 // the XC during an instruction's execution (specifically for instructions
101 // that have sideeffects that use the XC). Fix this.
102 bool in_syscall = this->thread->inSyscall;
103 this->thread->inSyscall = true;
104
105 this->fault = this->staticInst->initiateAcc(this, this->traceData);
106
107 this->thread->inSyscall = in_syscall;
108
109 return this->fault;
110 }
111
112 template <class Impl>
113 Fault
114 OzoneDynInst<Impl>::completeAcc()
115 {
116 if (this->isLoad()) {
117 this->fault = this->staticInst->completeAcc(this->req->data,
118 this,
119 this->traceData);
120 } else if (this->isStore()) {
121 this->fault = this->staticInst->completeAcc((uint8_t*)&this->req->result,
122 this,
123 this->traceData);
124 } else {
125 panic("Unknown type!");
126 }
127
128 return this->fault;
129 }
130
131 template <class Impl>
132 bool
133 OzoneDynInst<Impl>::srcInstReady(int regIdx)
134 {
135 return srcInsts[regIdx]->isResultReady();
136 }
137
138 template <class Impl>
139 void
140 OzoneDynInst<Impl>::addDependent(DynInstPtr &dependent_inst)
141 {
142 dependents.push_back(dependent_inst);
143 }
144
145 template <class Impl>
146 void
147 OzoneDynInst<Impl>::wakeDependents()
148 {
149 for (int i = 0; i < dependents.size(); ++i) {
150 dependents[i]->markSrcRegReady();
151 }
152 }
153
154 template <class Impl>
155 void
156 OzoneDynInst<Impl>::wakeMemDependents()
157 {
158 for (int i = 0; i < memDependents.size(); ++i) {
159 memDependents[i]->markMemInstReady(this);
160 }
161 }
162
163 template <class Impl>
164 void
165 OzoneDynInst<Impl>::markMemInstReady(OzoneDynInst<Impl> *inst)
166 {
167 ListIt mem_it = srcMemInsts.begin();
168 while ((*mem_it) != inst && mem_it != srcMemInsts.end()) {
169 mem_it++;
170 }
171 assert(mem_it != srcMemInsts.end());
172
173 srcMemInsts.erase(mem_it);
174 }
175
176 template <class Impl>
177 void
178 OzoneDynInst<Impl>::initInstPtrs()
179 {
180 for (int i = 0; i < MaxInstSrcRegs; ++i) {
181 srcInsts[i] = NULL;
182 }
183 iqItValid = false;
184 }
185
186 template <class Impl>
187 bool
188 OzoneDynInst<Impl>::srcsReady()
189 {
190 for (int i = 0; i < this->numSrcRegs(); ++i) {
191 if (!srcInsts[i]->isResultReady())
192 return false;
193 }
194
195 return true;
196 }
197
198 template <class Impl>
199 bool
200 OzoneDynInst<Impl>::eaSrcsReady()
201 {
202 for (int i = 1; i < this->numSrcRegs(); ++i) {
203 if (!srcInsts[i]->isResultReady())
204 return false;
205 }
206
207 return true;
208 }
209
210 template <class Impl>
211 void
212 OzoneDynInst<Impl>::clearDependents()
213 {
214 dependents.clear();
215 for (int i = 0; i < this->numSrcRegs(); ++i) {
216 srcInsts[i] = NULL;
217 }
218 for (int i = 0; i < this->numDestRegs(); ++i) {
219 prevDestInst[i] = NULL;
220 }
221 }
222
223 template <class Impl>
224 void
225 OzoneDynInst<Impl>::clearMemDependents()
226 {
227 memDependents.clear();
228 }
229
230 template <class Impl>
231 MiscReg
232 OzoneDynInst<Impl>::readMiscReg(int misc_reg)
233 {
234 return this->thread->readMiscReg(misc_reg);
235 }
236
237 template <class Impl>
238 MiscReg
239 OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault)
240 {
241 return this->thread->readMiscRegWithEffect(misc_reg, fault);
242 }
243
244 template <class Impl>
245 Fault
246 OzoneDynInst<Impl>::setMiscReg(int misc_reg, const MiscReg &val)
247 {
248 this->setIntResult(val);
249 return this->thread->setMiscReg(misc_reg, val);
250 }
251
252 template <class Impl>
253 Fault
254 OzoneDynInst<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
255 {
256 return this->thread->setMiscRegWithEffect(misc_reg, val);
257 }
258
259 #if FULL_SYSTEM
260
261 template <class Impl>
262 Fault
263 OzoneDynInst<Impl>::hwrei()
264 {
265 if (!this->cpu->inPalMode(this->readPC()))
266 return new AlphaISA::UnimplementedOpcodeFault;
267
268 this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR));
269
270 this->cpu->hwrei();
271
272 // FIXME: XXX check for interrupts? XXX
273 return NoFault;
274 }
275
276 template <class Impl>
277 int
278 OzoneDynInst<Impl>::readIntrFlag()
279 {
280 return this->cpu->readIntrFlag();
281 }
282
283 template <class Impl>
284 void
285 OzoneDynInst<Impl>::setIntrFlag(int val)
286 {
287 this->cpu->setIntrFlag(val);
288 }
289
290 template <class Impl>
291 bool
292 OzoneDynInst<Impl>::inPalMode()
293 {
294 return this->cpu->inPalMode();
295 }
296
297 template <class Impl>
298 void
299 OzoneDynInst<Impl>::trap(Fault fault)
300 {
301 fault->invoke(this->thread->getXCProxy());
302 }
303
304 template <class Impl>
305 bool
306 OzoneDynInst<Impl>::simPalCheck(int palFunc)
307 {
308 return this->cpu->simPalCheck(palFunc);
309 }
310 #else
311 template <class Impl>
312 void
313 OzoneDynInst<Impl>::syscall()
314 {
315 this->cpu->syscall();
316 }
317 #endif