src/cpu/ozone/front_end.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_FRONT_END_HH__
  32 #define __CPU_OZONE_FRONT_END_HH__
  33
  34 #include <deque>
  35
  36 #include "arch/utility.hh"
  37 #include "cpu/inst_seq.hh"
  38 #include "cpu/o3/bpred_unit.hh"
  39 #include "cpu/ozone/rename_table.hh"
  40 #include "mem/port.hh"
  41 #include "mem/request.hh"
  42 #include "sim/eventq.hh"
  43 #include "sim/stats.hh"
  44
  45 class ThreadContext;
  46 class MemObject;
  47 template <class>
  48 class OzoneThreadState;
  49 class PageTable;
  50 template <class>
  51 class TimeBuffer;
  52
  53 template <class Impl>
  54 class FrontEnd
  55 {
  56   public:
  57     typedef typename Impl::Params Params;
  58     typedef typename Impl::DynInst DynInst;
  59     typedef typename Impl::DynInstPtr DynInstPtr;
  60     typedef typename Impl::CPUType CPUType;
  61     typedef typename Impl::BackEnd BackEnd;
  62
  63     typedef typename Impl::CPUType::OzoneTC OzoneTC;
  64     typedef typename Impl::CPUType::CommStruct CommStruct;
  65
  66     /** IcachePort class.  Handles doing the communication with the
  67      * cache/memory.
  68      */
  69     class IcachePort : public Port
  70     {
  71       protected:
  72         /** Pointer to FE. */
  73         FrontEnd<Impl> *fe;
  74
  75       public:
  76         /** Default constructor. */
  77         IcachePort(FrontEnd<Impl> *_fe)
  78             : fe(_fe)
  79         { }
  80
  81       protected:
  82         /** Atomic version of receive.  Panics. */
  83         virtual Tick recvAtomic(PacketPtr pkt);
  84
  85         /** Functional version of receive.  Panics. */
  86         virtual void recvFunctional(PacketPtr pkt);
  87
  88         /** Receives status change.  Other than range changing, panics. */
  89         virtual void recvStatusChange(Status status);
  90
  91         /** Returns the address ranges of this device. */
  92         virtual void getDeviceAddressRanges(AddrRangeList &resp,
  93                                             AddrRangeList &snoop)
  94         { resp.clear(); snoop.clear(); }
  95
  96         /** Timing version of receive.  Handles setting fetch to the
  97          * proper status to start fetching. */
  98         virtual bool recvTiming(PacketPtr pkt);
  99
 100         /** Handles doing a retry of a failed fetch. */
 101         virtual void recvRetry();
 102     };
 103
 104     FrontEnd(Params *params);
 105
 106     std::string name() const;
 107
 108     void setCPU(CPUType *cpu_ptr);
 109
 110     void setBackEnd(BackEnd *back_end_ptr)
 111     { backEnd = back_end_ptr; }
 112
 113     void setCommBuffer(TimeBuffer<CommStruct> *_comm);
 114
 115     void setTC(ThreadContext *tc_ptr);
 116
 117     void setThreadState(OzoneThreadState<Impl> *thread_ptr)
 118     { thread = thread_ptr; }
 119
 120     void regStats();
 121
 122     Port *getIcachePort() { return &icachePort; }
 123
 124     void tick();
 125     Fault fetchCacheLine();
 126     void processInst(DynInstPtr &inst);
 127     void squash(const InstSeqNum &squash_num, const Addr &next_PC,
 128                 const bool is_branch = false, const bool branch_taken = false);
 129     DynInstPtr getInst();
 130
 131     void processCacheCompletion(Packet *pkt);
 132
 133     void addFreeRegs(int num_freed);
 134
 135     bool isEmpty() { return instBuffer.empty(); }
 136
 137     void switchOut();
 138
 139     void doSwitchOut();
 140
 141     void takeOverFrom(ThreadContext *old_tc = NULL);
 142
 143     bool isSwitchedOut() { return switchedOut; }
 144
 145     bool switchedOut;
 146
 147   private:
 148     void recvRetry();
 149
 150     bool updateStatus();
 151
 152     void checkBE();
 153     DynInstPtr getInstFromCacheline();
 154     void renameInst(DynInstPtr &inst);
 155     // Returns true if we need to stop the front end this cycle
 156     bool processBarriers(DynInstPtr &inst);
 157
 158     void handleFault(Fault &fault);
 159   public:
 160     Fault getFault() { return fetchFault; }
 161   private:
 162     Fault fetchFault;
 163
 164     // Align an address (typically a PC) to the start of an I-cache block.
 165     // We fold in the PISA 64- to 32-bit conversion here as well.
 166     Addr icacheBlockAlignPC(Addr addr)
 167     {
 168         addr = TheISA::realPCToFetchPC(addr);
 169         return (addr & ~(cacheBlkMask));
 170     }
 171
 172     InstSeqNum getAndIncrementInstSeq()
 173     { return cpu->globalSeqNum++; }
 174
 175   public:
 176     CPUType *cpu;
 177
 178     BackEnd *backEnd;
 179
 180     ThreadContext *tc;
 181
 182     OzoneThreadState<Impl> *thread;
 183
 184     enum Status {
 185         Running,
 186         Idle,
 187         IcacheWaitResponse,
 188         IcacheWaitRetry,
 189         IcacheAccessComplete,
 190         SerializeBlocked,
 191         SerializeComplete,
 192         RenameBlocked,
 193         QuiescePending,
 194         TrapPending,
 195         BEBlocked
 196     };
 197
 198     Status status;
 199
 200   private:
 201     TimeBuffer<CommStruct> *comm;
 202     typename TimeBuffer<CommStruct>::wire fromCommit;
 203
 204     typedef typename Impl::BranchPred BranchPred;
 205
 206     BranchPred branchPred;
 207
 208     IcachePort icachePort;
 209
 210     MemObject *mem;
 211
 212     RequestPtr memReq;
 213
 214     /** Mask to get a cache block's address. */
 215     Addr cacheBlkMask;
 216
 217     unsigned cacheBlkSize;
 218
 219     Addr cacheBlkPC;
 220
 221     /** The cache line being fetched. */
 222     uint8_t *cacheData;
 223
 224     bool fetchCacheLineNextCycle;
 225
 226     bool cacheBlkValid;
 227
 228     bool cacheBlocked;
 229
 230     /** The packet that is waiting to be retried. */
 231     PacketPtr retryPkt;
 232
 233   public:
 234     RenameTable<Impl> renameTable;
 235
 236   private:
 237     Addr PC;
 238     Addr nextPC;
 239
 240   public:
 241     void setPC(Addr val) { PC = val; }
 242     void setNextPC(Addr val) { nextPC = val; }
 243
 244     void wakeFromQuiesce();
 245
 246     void dumpInsts();
 247
 248   private:
 249     typedef typename std::deque<DynInstPtr> InstBuff;
 250     typedef typename InstBuff::iterator InstBuffIt;
 251
 252     InstBuff instBuffer;
 253
 254     int instBufferSize;
 255
 256     int maxInstBufferSize;
 257
 258     int width;
 259
 260     int freeRegs;
 261
 262     int numPhysRegs;
 263
 264     bool serializeNext;
 265
 266     DynInstPtr barrierInst;
 267
 268   public:
 269     bool interruptPending;
 270   private:
 271     // number of idle cycles
 272 /*
 273     Stats::Average<> notIdleFraction;
 274     Stats::Formula idleFraction;
 275 */
 276     // @todo: Consider making these vectors and tracking on a per thread basis.
 277     /** Stat for total number of cycles stalled due to an icache miss. */
 278     Stats::Scalar<> icacheStallCycles;
 279     /** Stat for total number of fetched instructions. */
 280     Stats::Scalar<> fetchedInsts;
 281     Stats::Scalar<> fetchedBranches;
 282     /** Stat for total number of predicted branches. */
 283     Stats::Scalar<> predictedBranches;
 284     /** Stat for total number of cycles spent fetching. */
 285     Stats::Scalar<> fetchCycles;
 286
 287     Stats::Scalar<> fetchIdleCycles;
 288     /** Stat for total number of cycles spent squashing. */
 289     Stats::Scalar<> fetchSquashCycles;
 290     /** Stat for total number of cycles spent blocked due to other stages in
 291      * the pipeline.
 292      */
 293     Stats::Scalar<> fetchBlockedCycles;
 294     /** Stat for total number of fetched cache lines. */
 295     Stats::Scalar<> fetchedCacheLines;
 296
 297     Stats::Scalar<> fetchIcacheSquashes;
 298     /** Distribution of number of instructions fetched each cycle. */
 299     Stats::Distribution<> fetchNisnDist;
 300 //    Stats::Vector<> qfull_iq_occupancy;
 301 //    Stats::VectorDistribution<> qfull_iq_occ_dist_;
 302     Stats::Formula idleRate;
 303     Stats::Formula branchRate;
 304     Stats::Formula fetchRate;
 305     Stats::Scalar<> IFQCount;   // cumulative IFQ occupancy
 306     Stats::Formula IFQOccupancy;
 307     Stats::Formula IFQLatency;
 308     Stats::Scalar<> IFQFcount; // cumulative IFQ full count
 309     Stats::Formula IFQFullRate;
 310
 311     Stats::Scalar<> dispatchCountStat;
 312     Stats::Scalar<> dispatchedSerializing;
 313     Stats::Scalar<> dispatchedTempSerializing;
 314     Stats::Scalar<> dispatchSerializeStallCycles;
 315     Stats::Formula dispatchRate;
 316     Stats::Formula regIntFull;
 317     Stats::Formula regFpFull;
 318 };
 319
 320 #endif // __CPU_OZONE_FRONT_END_HH__