src/cpu/ozone/front_end.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_FRONT_END_HH__
  32 #define __CPU_OZONE_FRONT_END_HH__
  33
  34 #include <deque>
  35
  36 #include "arch/utility.hh"
  37 #include "base/timebuf.hh"
  38 #include "cpu/inst_seq.hh"
  39 #include "cpu/o3/bpred_unit.hh"
  40 #include "cpu/ozone/rename_table.hh"
  41 #include "mem/port.hh"
  42 #include "mem/request.hh"
  43 #include "sim/eventq.hh"
  44 #include "sim/stats.hh"
  45
  46 class ThreadContext;
  47 class MemObject;
  48 template <class>
  49 class OzoneThreadState;
  50 class PageTable;
  51 template <class>
  52 class TimeBuffer;
  53
  54 template <class Impl>
  55 class FrontEnd
  56 {
  57   public:
  58     typedef typename Impl::Params Params;
  59     typedef typename Impl::DynInst DynInst;
  60     typedef typename Impl::DynInstPtr DynInstPtr;
  61     typedef typename Impl::CPUType CPUType;
  62     typedef typename Impl::BackEnd BackEnd;
  63
  64     typedef typename Impl::CPUType::OzoneTC OzoneTC;
  65     typedef typename Impl::CPUType::CommStruct CommStruct;
  66
  67     /** IcachePort class.  Handles doing the communication with the
  68      * cache/memory.
  69      */
  70     class IcachePort : public Port
  71     {
  72       protected:
  73         /** Pointer to FE. */
  74         FrontEnd<Impl> *fe;
  75
  76       public:
  77         /** Default constructor. */
  78         IcachePort(FrontEnd<Impl> *_fe)
  79             : fe(_fe)
  80         { }
  81
  82       protected:
  83         /** Atomic version of receive.  Panics. */
  84         virtual Tick recvAtomic(PacketPtr pkt);
  85
  86         /** Functional version of receive.  Panics. */
  87         virtual void recvFunctional(PacketPtr pkt);
  88
  89         /** Receives status change.  Other than range changing, panics. */
  90         virtual void recvStatusChange(Status status);
  91
  92         /** Returns the address ranges of this device. */
  93         virtual void getDeviceAddressRanges(AddrRangeList &resp,
  94                                             AddrRangeList &snoop)
  95         { resp.clear(); snoop.clear(); }
  96
  97         /** Timing version of receive.  Handles setting fetch to the
  98          * proper status to start fetching. */
  99         virtual bool recvTiming(PacketPtr pkt);
 100
 101         /** Handles doing a retry of a failed fetch. */
 102         virtual void recvRetry();
 103     };
 104
 105     FrontEnd(Params *params);
 106
 107     std::string name() const;
 108
 109     void setCPU(CPUType *cpu_ptr);
 110
 111     void setBackEnd(BackEnd *back_end_ptr)
 112     { backEnd = back_end_ptr; }
 113
 114     void setCommBuffer(TimeBuffer<CommStruct> *_comm);
 115
 116     void setTC(ThreadContext *tc_ptr);
 117
 118     void setThreadState(OzoneThreadState<Impl> *thread_ptr)
 119     { thread = thread_ptr; }
 120
 121     void regStats();
 122
 123     Port *getIcachePort() { return &icachePort; }
 124
 125     void tick();
 126     Fault fetchCacheLine();
 127     void processInst(DynInstPtr &inst);
 128     void squash(const InstSeqNum &squash_num, const Addr &next_PC,
 129                 const bool is_branch = false, const bool branch_taken = false);
 130     DynInstPtr getInst();
 131
 132     void processCacheCompletion(Packet *pkt);
 133
 134     void addFreeRegs(int num_freed);
 135
 136     bool isEmpty() { return instBuffer.empty(); }
 137
 138     void switchOut();
 139
 140     void doSwitchOut();
 141
 142     void takeOverFrom(ThreadContext *old_tc = NULL);
 143
 144     bool isSwitchedOut() { return switchedOut; }
 145
 146     bool switchedOut;
 147
 148   private:
 149     void recvRetry();
 150
 151     bool updateStatus();
 152
 153     void checkBE();
 154     DynInstPtr getInstFromCacheline();
 155     void renameInst(DynInstPtr &inst);
 156     // Returns true if we need to stop the front end this cycle
 157     bool processBarriers(DynInstPtr &inst);
 158
 159     void handleFault(Fault &fault);
 160   public:
 161     Fault getFault() { return fetchFault; }
 162   private:
 163     Fault fetchFault;
 164
 165     // Align an address (typically a PC) to the start of an I-cache block.
 166     // We fold in the PISA 64- to 32-bit conversion here as well.
 167     Addr icacheBlockAlignPC(Addr addr)
 168     {
 169         addr = TheISA::realPCToFetchPC(addr);
 170         return (addr & ~(cacheBlkMask));
 171     }
 172
 173     InstSeqNum getAndIncrementInstSeq()
 174     { return cpu->globalSeqNum++; }
 175
 176   public:
 177     CPUType *cpu;
 178
 179     BackEnd *backEnd;
 180
 181     ThreadContext *tc;
 182
 183     OzoneThreadState<Impl> *thread;
 184
 185     enum Status {
 186         Running,
 187         Idle,
 188         IcacheWaitResponse,
 189         IcacheWaitRetry,
 190         IcacheAccessComplete,
 191         SerializeBlocked,
 192         SerializeComplete,
 193         RenameBlocked,
 194         QuiescePending,
 195         TrapPending,
 196         BEBlocked
 197     };
 198
 199     Status status;
 200
 201   private:
 202     TimeBuffer<CommStruct> *comm;
 203     typename TimeBuffer<CommStruct>::wire fromCommit;
 204
 205     typedef typename Impl::BranchPred BranchPred;
 206
 207     BranchPred branchPred;
 208
 209     IcachePort icachePort;
 210
 211     MemObject *mem;
 212
 213     RequestPtr memReq;
 214
 215     /** Mask to get a cache block's address. */
 216     Addr cacheBlkMask;
 217
 218     unsigned cacheBlkSize;
 219
 220     Addr cacheBlkPC;
 221
 222     /** The cache line being fetched. */
 223     uint8_t *cacheData;
 224
 225     bool fetchCacheLineNextCycle;
 226
 227     bool cacheBlkValid;
 228
 229     bool cacheBlocked;
 230
 231     /** The packet that is waiting to be retried. */
 232     PacketPtr retryPkt;
 233
 234   public:
 235     RenameTable<Impl> renameTable;
 236
 237   private:
 238     Addr PC;
 239     Addr nextPC;
 240
 241   public:
 242     void setPC(Addr val) { PC = val; }
 243     void setNextPC(Addr val) { nextPC = val; }
 244
 245     void wakeFromQuiesce();
 246
 247     void dumpInsts();
 248
 249   private:
 250     TimeBuffer<int> numInstsReady;
 251
 252     typedef typename std::deque<DynInstPtr> InstBuff;
 253     typedef typename InstBuff::iterator InstBuffIt;
 254
 255     InstBuff feBuffer;
 256
 257     InstBuff instBuffer;
 258
 259     int instBufferSize;
 260
 261     int maxInstBufferSize;
 262
 263     int latency;
 264
 265     int width;
 266
 267     int freeRegs;
 268
 269     int numPhysRegs;
 270
 271     bool serializeNext;
 272
 273     DynInstPtr barrierInst;
 274
 275   public:
 276     bool interruptPending;
 277   private:
 278     // number of idle cycles
 279 /*
 280     Stats::Average<> notIdleFraction;
 281     Stats::Formula idleFraction;
 282 */
 283     // @todo: Consider making these vectors and tracking on a per thread basis.
 284     /** Stat for total number of cycles stalled due to an icache miss. */
 285     Stats::Scalar<> icacheStallCycles;
 286     /** Stat for total number of fetched instructions. */
 287     Stats::Scalar<> fetchedInsts;
 288     Stats::Scalar<> fetchedBranches;
 289     /** Stat for total number of predicted branches. */
 290     Stats::Scalar<> predictedBranches;
 291     /** Stat for total number of cycles spent fetching. */
 292     Stats::Scalar<> fetchCycles;
 293
 294     Stats::Scalar<> fetchIdleCycles;
 295     /** Stat for total number of cycles spent squashing. */
 296     Stats::Scalar<> fetchSquashCycles;
 297     /** Stat for total number of cycles spent blocked due to other stages in
 298      * the pipeline.
 299      */
 300     Stats::Scalar<> fetchBlockedCycles;
 301     /** Stat for total number of fetched cache lines. */
 302     Stats::Scalar<> fetchedCacheLines;
 303
 304     Stats::Scalar<> fetchIcacheSquashes;
 305     /** Distribution of number of instructions fetched each cycle. */
 306     Stats::Distribution<> fetchNisnDist;
 307 //    Stats::Vector<> qfull_iq_occupancy;
 308 //    Stats::VectorDistribution<> qfull_iq_occ_dist_;
 309     Stats::Formula idleRate;
 310     Stats::Formula branchRate;
 311     Stats::Formula fetchRate;
 312     Stats::Scalar<> IFQCount;   // cumulative IFQ occupancy
 313     Stats::Formula IFQOccupancy;
 314     Stats::Formula IFQLatency;
 315     Stats::Scalar<> IFQFcount; // cumulative IFQ full count
 316     Stats::Formula IFQFullRate;
 317
 318     Stats::Scalar<> dispatchCountStat;
 319     Stats::Scalar<> dispatchedSerializing;
 320     Stats::Scalar<> dispatchedTempSerializing;
 321     Stats::Scalar<> dispatchSerializeStallCycles;
 322     Stats::Formula dispatchRate;
 323     Stats::Formula regIntFull;
 324     Stats::Formula regFpFull;
 325 };
 326
 327 #endif // __CPU_OZONE_FRONT_END_HH__