src/cpu/ozone/front_end.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_FRONT_END_HH__
  32 #define __CPU_OZONE_FRONT_END_HH__
  33
  34 #include <deque>
  35
  36 #include "arch/utility.hh"
  37 #include "config/the_isa.hh"
  38 #include "cpu/o3/bpred_unit.hh"
  39 #include "cpu/ozone/rename_table.hh"
  40 #include "cpu/inst_seq.hh"
  41 #include "cpu/timebuf.hh"
  42 #include "mem/port.hh"
  43 #include "mem/request.hh"
  44 #include "sim/eventq.hh"
  45 #include "sim/stats.hh"
  46
  47 class ThreadContext;
  48 class MemObject;
  49 template <class>
  50 class OzoneThreadState;
  51 class PageTable;
  52 template <class>
  53 class TimeBuffer;
  54
  55 template <class Impl>
  56 class FrontEnd
  57 {
  58   public:
  59     typedef typename Impl::Params Params;
  60     typedef typename Impl::DynInst DynInst;
  61     typedef typename Impl::DynInstPtr DynInstPtr;
  62     typedef typename Impl::CPUType CPUType;
  63     typedef typename Impl::BackEnd BackEnd;
  64
  65     typedef typename Impl::CPUType::OzoneTC OzoneTC;
  66     typedef typename Impl::CPUType::CommStruct CommStruct;
  67
  68     /** IcachePort class.  Handles doing the communication with the
  69      * cache/memory.
  70      */
  71     class IcachePort : public MasterPort
  72     {
  73       protected:
  74         /** Pointer to FE. */
  75         FrontEnd<Impl> *fe;
  76
  77       public:
  78         /** Default constructor. */
  79         IcachePort(FrontEnd<Impl> *_fe)
  80             : fe(_fe)
  81         { }
  82
  83       protected:
  84         /** Atomic version of receive.  Panics. */
  85         virtual Tick recvAtomic(PacketPtr pkt);
  86
  87         /** Functional version of receive.  Panics. */
  88         virtual void recvFunctional(PacketPtr pkt);
  89
  90         /** Timing version of receive.  Handles setting fetch to the
  91          * proper status to start fetching. */
  92         virtual bool recvTiming(PacketPtr pkt);
  93
  94         /** Handles doing a retry of a failed fetch. */
  95         virtual void recvRetry();
  96     };
  97
  98     FrontEnd(Params *params);
  99
 100     std::string name() const;
 101
 102     void setCPU(CPUType *cpu_ptr);
 103
 104     void setBackEnd(BackEnd *back_end_ptr)
 105     { backEnd = back_end_ptr; }
 106
 107     void setCommBuffer(TimeBuffer<CommStruct> *_comm);
 108
 109     void setTC(ThreadContext *tc_ptr);
 110
 111     void setThreadState(OzoneThreadState<Impl> *thread_ptr)
 112     { thread = thread_ptr; }
 113
 114     void regStats();
 115
 116     Port *getIcachePort() { return &icachePort; }
 117
 118     void tick();
 119     Fault fetchCacheLine();
 120     void processInst(DynInstPtr &inst);
 121     void squash(const InstSeqNum &squash_num, const Addr &next_PC,
 122                 const bool is_branch = false, const bool branch_taken = false);
 123     DynInstPtr getInst();
 124
 125     void processCacheCompletion(PacketPtr pkt);
 126
 127     void addFreeRegs(int num_freed);
 128
 129     bool isEmpty() { return instBuffer.empty(); }
 130
 131     void switchOut();
 132
 133     void doSwitchOut();
 134
 135     void takeOverFrom(ThreadContext *old_tc = NULL);
 136
 137     bool isSwitchedOut() { return switchedOut; }
 138
 139     bool switchedOut;
 140
 141   private:
 142     void recvRetry();
 143
 144     bool updateStatus();
 145
 146     void checkBE();
 147     DynInstPtr getInstFromCacheline();
 148     void renameInst(DynInstPtr &inst);
 149     // Returns true if we need to stop the front end this cycle
 150     bool processBarriers(DynInstPtr &inst);
 151
 152     void handleFault(Fault &fault);
 153   public:
 154     Fault getFault() { return fetchFault; }
 155   private:
 156     Fault fetchFault;
 157
 158     // Align an address (typically a PC) to the start of an I-cache block.
 159     // We fold in the PISA 64- to 32-bit conversion here as well.
 160     Addr icacheBlockAlignPC(Addr addr)
 161     {
 162         return (addr & ~(cacheBlkMask));
 163     }
 164
 165     InstSeqNum getAndIncrementInstSeq()
 166     { return cpu->globalSeqNum++; }
 167
 168   public:
 169     CPUType *cpu;
 170
 171     BackEnd *backEnd;
 172
 173     ThreadContext *tc;
 174
 175     OzoneThreadState<Impl> *thread;
 176
 177     enum Status {
 178         Running,
 179         Idle,
 180         IcacheWaitResponse,
 181         IcacheWaitRetry,
 182         IcacheAccessComplete,
 183         SerializeBlocked,
 184         SerializeComplete,
 185         RenameBlocked,
 186         QuiescePending,
 187         TrapPending,
 188         BEBlocked
 189     };
 190
 191     Status status;
 192
 193   private:
 194     TimeBuffer<CommStruct> *comm;
 195     typename TimeBuffer<CommStruct>::wire fromCommit;
 196
 197     typedef typename Impl::BranchPred BranchPred;
 198
 199     BranchPred branchPred;
 200
 201     IcachePort icachePort;
 202
 203     RequestPtr memReq;
 204
 205     /** Mask to get a cache block's address. */
 206     Addr cacheBlkMask;
 207
 208     unsigned cacheBlkSize;
 209
 210     Addr cacheBlkPC;
 211
 212     /** The cache line being fetched. */
 213     uint8_t *cacheData;
 214
 215     bool fetchCacheLineNextCycle;
 216
 217     bool cacheBlkValid;
 218
 219     bool cacheBlocked;
 220
 221     /** The packet that is waiting to be retried. */
 222     PacketPtr retryPkt;
 223
 224   public:
 225     RenameTable<Impl> renameTable;
 226
 227   private:
 228     Addr PC;
 229     Addr nextPC;
 230
 231   public:
 232     void setPC(Addr val) { PC = val; }
 233     void setNextPC(Addr val) { nextPC = val; }
 234
 235     void wakeFromQuiesce();
 236
 237     void dumpInsts();
 238
 239   private:
 240     TimeBuffer<int> numInstsReady;
 241
 242     typedef typename std::deque<DynInstPtr> InstBuff;
 243     typedef typename InstBuff::iterator InstBuffIt;
 244
 245     InstBuff feBuffer;
 246
 247     InstBuff instBuffer;
 248
 249     int instBufferSize;
 250
 251     int maxInstBufferSize;
 252
 253     int latency;
 254
 255     int width;
 256
 257     int freeRegs;
 258
 259     int numPhysRegs;
 260
 261     bool serializeNext;
 262
 263     DynInstPtr barrierInst;
 264
 265   public:
 266     bool interruptPending;
 267   private:
 268     // number of idle cycles
 269 /*
 270     Stats::Average notIdleFraction;
 271     Stats::Formula idleFraction;
 272 */
 273     // @todo: Consider making these vectors and tracking on a per thread basis.
 274     /** Stat for total number of cycles stalled due to an icache miss. */
 275     Stats::Scalar icacheStallCycles;
 276     /** Stat for total number of fetched instructions. */
 277     Stats::Scalar fetchedInsts;
 278     Stats::Scalar fetchedBranches;
 279     /** Stat for total number of predicted branches. */
 280     Stats::Scalar predictedBranches;
 281     /** Stat for total number of cycles spent fetching. */
 282     Stats::Scalar fetchCycles;
 283
 284     Stats::Scalar fetchIdleCycles;
 285     /** Stat for total number of cycles spent squashing. */
 286     Stats::Scalar fetchSquashCycles;
 287     /** Stat for total number of cycles spent blocked due to other stages in
 288      * the pipeline.
 289      */
 290     Stats::Scalar fetchBlockedCycles;
 291     /** Stat for total number of fetched cache lines. */
 292     Stats::Scalar fetchedCacheLines;
 293
 294     Stats::Scalar fetchIcacheSquashes;
 295     /** Distribution of number of instructions fetched each cycle. */
 296     Stats::Distribution fetchNisnDist;
 297 //    Stats::Vector qfull_iq_occupancy;
 298 //    Stats::VectorDistribution qfull_iq_occ_dist_;
 299     Stats::Formula idleRate;
 300     Stats::Formula branchRate;
 301     Stats::Formula fetchRate;
 302     Stats::Scalar IFQCount;   // cumulative IFQ occupancy
 303     Stats::Formula IFQOccupancy;
 304     Stats::Formula IFQLatency;
 305     Stats::Scalar IFQFcount; // cumulative IFQ full count
 306     Stats::Formula IFQFullRate;
 307
 308     Stats::Scalar dispatchCountStat;
 309     Stats::Scalar dispatchedSerializing;
 310     Stats::Scalar dispatchedTempSerializing;
 311     Stats::Scalar dispatchSerializeStallCycles;
 312     Stats::Formula dispatchRate;
 313     Stats::Formula regIntFull;
 314     Stats::Formula regFpFull;
 315 };
 316
 317 #endif // __CPU_OZONE_FRONT_END_HH__