2 * Copyright (c) 2006 The Regents of The University of Michigan
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31 #ifndef __CPU_OZONE_FRONT_END_HH__
32 #define __CPU_OZONE_FRONT_END_HH__
36 #include "arch/utility.hh"
37 #include "config/the_isa.hh"
38 #include "cpu/o3/bpred_unit.hh"
39 #include "cpu/ozone/rename_table.hh"
40 #include "cpu/inst_seq.hh"
41 #include "cpu/timebuf.hh"
42 #include "mem/port.hh"
43 #include "mem/request.hh"
44 #include "sim/eventq.hh"
45 #include "sim/stats.hh"
50 class OzoneThreadState;
59 typedef typename Impl::Params Params;
60 typedef typename Impl::DynInst DynInst;
61 typedef typename Impl::DynInstPtr DynInstPtr;
62 typedef typename Impl::CPUType CPUType;
63 typedef typename Impl::BackEnd BackEnd;
65 typedef typename Impl::CPUType::OzoneTC OzoneTC;
66 typedef typename Impl::CPUType::CommStruct CommStruct;
68 /** IcachePort class. Handles doing the communication with the
71 class IcachePort : public MasterPort
78 /** Default constructor. */
79 IcachePort(FrontEnd<Impl> *_fe)
84 /** Atomic version of receive. Panics. */
85 virtual Tick recvAtomic(PacketPtr pkt);
87 /** Functional version of receive. Panics. */
88 virtual void recvFunctional(PacketPtr pkt);
90 /** Timing version of receive. Handles setting fetch to the
91 * proper status to start fetching. */
92 virtual bool recvTiming(PacketPtr pkt);
94 /** Handles doing a retry of a failed fetch. */
95 virtual void recvRetry();
98 FrontEnd(Params *params);
100 std::string name() const;
102 void setCPU(CPUType *cpu_ptr);
104 void setBackEnd(BackEnd *back_end_ptr)
105 { backEnd = back_end_ptr; }
107 void setCommBuffer(TimeBuffer<CommStruct> *_comm);
109 void setTC(ThreadContext *tc_ptr);
111 void setThreadState(OzoneThreadState<Impl> *thread_ptr)
112 { thread = thread_ptr; }
116 Port *getIcachePort() { return &icachePort; }
119 Fault fetchCacheLine();
120 void processInst(DynInstPtr &inst);
121 void squash(const InstSeqNum &squash_num, const Addr &next_PC,
122 const bool is_branch = false, const bool branch_taken = false);
123 DynInstPtr getInst();
125 void processCacheCompletion(PacketPtr pkt);
127 void addFreeRegs(int num_freed);
129 bool isEmpty() { return instBuffer.empty(); }
135 void takeOverFrom(ThreadContext *old_tc = NULL);
137 bool isSwitchedOut() { return switchedOut; }
147 DynInstPtr getInstFromCacheline();
148 void renameInst(DynInstPtr &inst);
149 // Returns true if we need to stop the front end this cycle
150 bool processBarriers(DynInstPtr &inst);
152 void handleFault(Fault &fault);
154 Fault getFault() { return fetchFault; }
158 // Align an address (typically a PC) to the start of an I-cache block.
159 // We fold in the PISA 64- to 32-bit conversion here as well.
160 Addr icacheBlockAlignPC(Addr addr)
162 return (addr & ~(cacheBlkMask));
165 InstSeqNum getAndIncrementInstSeq()
166 { return cpu->globalSeqNum++; }
175 OzoneThreadState<Impl> *thread;
182 IcacheAccessComplete,
194 TimeBuffer<CommStruct> *comm;
195 typename TimeBuffer<CommStruct>::wire fromCommit;
197 typedef typename Impl::BranchPred BranchPred;
199 BranchPred branchPred;
201 IcachePort icachePort;
205 /** Mask to get a cache block's address. */
208 unsigned cacheBlkSize;
212 /** The cache line being fetched. */
215 bool fetchCacheLineNextCycle;
221 /** The packet that is waiting to be retried. */
225 RenameTable<Impl> renameTable;
232 void setPC(Addr val) { PC = val; }
233 void setNextPC(Addr val) { nextPC = val; }
235 void wakeFromQuiesce();
240 TimeBuffer<int> numInstsReady;
242 typedef typename std::deque<DynInstPtr> InstBuff;
243 typedef typename InstBuff::iterator InstBuffIt;
251 int maxInstBufferSize;
263 DynInstPtr barrierInst;
266 bool interruptPending;
268 // number of idle cycles
270 Stats::Average notIdleFraction;
271 Stats::Formula idleFraction;
273 // @todo: Consider making these vectors and tracking on a per thread basis.
274 /** Stat for total number of cycles stalled due to an icache miss. */
275 Stats::Scalar icacheStallCycles;
276 /** Stat for total number of fetched instructions. */
277 Stats::Scalar fetchedInsts;
278 Stats::Scalar fetchedBranches;
279 /** Stat for total number of predicted branches. */
280 Stats::Scalar predictedBranches;
281 /** Stat for total number of cycles spent fetching. */
282 Stats::Scalar fetchCycles;
284 Stats::Scalar fetchIdleCycles;
285 /** Stat for total number of cycles spent squashing. */
286 Stats::Scalar fetchSquashCycles;
287 /** Stat for total number of cycles spent blocked due to other stages in
290 Stats::Scalar fetchBlockedCycles;
291 /** Stat for total number of fetched cache lines. */
292 Stats::Scalar fetchedCacheLines;
294 Stats::Scalar fetchIcacheSquashes;
295 /** Distribution of number of instructions fetched each cycle. */
296 Stats::Distribution fetchNisnDist;
297 // Stats::Vector qfull_iq_occupancy;
298 // Stats::VectorDistribution qfull_iq_occ_dist_;
299 Stats::Formula idleRate;
300 Stats::Formula branchRate;
301 Stats::Formula fetchRate;
302 Stats::Scalar IFQCount; // cumulative IFQ occupancy
303 Stats::Formula IFQOccupancy;
304 Stats::Formula IFQLatency;
305 Stats::Scalar IFQFcount; // cumulative IFQ full count
306 Stats::Formula IFQFullRate;
308 Stats::Scalar dispatchCountStat;
309 Stats::Scalar dispatchedSerializing;
310 Stats::Scalar dispatchedTempSerializing;
311 Stats::Scalar dispatchSerializeStallCycles;
312 Stats::Formula dispatchRate;
313 Stats::Formula regIntFull;
314 Stats::Formula regFpFull;
317 #endif // __CPU_OZONE_FRONT_END_HH__