src/cpu/ozone/front_end_impl.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "arch/isa_traits.hh"
  32 #include "arch/utility.hh"
  33 #include "base/statistics.hh"
  34 #include "config/the_isa.hh"
  35 #include "config/use_checker.hh"
  36 #include "cpu/ozone/front_end.hh"
  37 #include "cpu/exetrace.hh"
  38 #include "cpu/thread_context.hh"
  39 #include "mem/mem_object.hh"
  40 #include "mem/packet.hh"
  41 #include "mem/request.hh"
  42 #include "sim/faults.hh"
  43
  44 #if USE_CHECKER
  45 #include "cpu/checker/cpu.hh"
  46 #endif
  47
  48 using namespace TheISA;
  49
  50 template<class Impl>
  51 Tick
  52 FrontEnd<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
  53 {
  54     panic("FrontEnd doesn't expect recvAtomic callback!");
  55     return curTick();
  56 }
  57
  58 template<class Impl>
  59 void
  60 FrontEnd<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
  61 {
  62     warn("FrontEnd doesn't update state from functional calls");
  63 }
  64
  65 template<class Impl>
  66 void
  67 FrontEnd<Impl>::IcachePort::recvStatusChange(Status status)
  68 {
  69     if (status == RangeChange)
  70         return;
  71
  72     panic("FrontEnd doesn't expect recvStatusChange callback!");
  73 }
  74
  75 template<class Impl>
  76 bool
  77 FrontEnd<Impl>::IcachePort::recvTiming(PacketPtr pkt)
  78 {
  79     fe->processCacheCompletion(pkt);
  80     return true;
  81 }
  82
  83 template<class Impl>
  84 void
  85 FrontEnd<Impl>::IcachePort::recvRetry()
  86 {
  87     fe->recvRetry();
  88 }
  89
  90 template <class Impl>
  91 FrontEnd<Impl>::FrontEnd(Params *params)
  92     : branchPred(params),
  93       icachePort(this),
  94       numInstsReady(params->frontEndLatency, 0),
  95       instBufferSize(0),
  96       maxInstBufferSize(params->maxInstBufferSize),
  97       latency(params->frontEndLatency),
  98       width(params->frontEndWidth),
  99       freeRegs(params->numPhysicalRegs),
 100       numPhysRegs(params->numPhysicalRegs),
 101       serializeNext(false),
 102       interruptPending(false)
 103 {
 104     switchedOut = false;
 105
 106     status = Idle;
 107
 108     memReq = NULL;
 109     // Size of cache block.
 110     cacheBlkSize = 64;
 111
 112     assert(isPowerOf2(cacheBlkSize));
 113
 114     // Create mask to get rid of offset bits.
 115     cacheBlkMask = (cacheBlkSize - 1);
 116
 117     // Create space to store a cache line.
 118     cacheData = new uint8_t[cacheBlkSize];
 119
 120     fetchCacheLineNextCycle = true;
 121
 122     cacheBlkValid = cacheBlocked = false;
 123
 124     retryPkt = NULL;
 125
 126     fetchFault = NoFault;
 127 }
 128
 129 template <class Impl>
 130 std::string
 131 FrontEnd<Impl>::name() const
 132 {
 133     return cpu->name() + ".frontend";
 134 }
 135
 136 template <class Impl>
 137 void
 138 FrontEnd<Impl>::setCPU(CPUType *cpu_ptr)
 139 {
 140     cpu = cpu_ptr;
 141
 142     icachePort.setName(this->name() + "-iport");
 143
 144 #if USE_CHECKER
 145     if (cpu->checker) {
 146         cpu->checker->setIcachePort(&icachePort);
 147     }
 148 #endif
 149 }
 150
 151 template <class Impl>
 152 void
 153 FrontEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
 154 {
 155     comm = _comm;
 156     // @todo: Hardcoded for now.  Allow this to be set by a latency.
 157     fromCommit = comm->getWire(-1);
 158 }
 159
 160 template <class Impl>
 161 void
 162 FrontEnd<Impl>::setTC(ThreadContext *tc_ptr)
 163 {
 164     tc = tc_ptr;
 165 }
 166
 167 template <class Impl>
 168 void
 169 FrontEnd<Impl>::regStats()
 170 {
 171     icacheStallCycles
 172         .name(name() + ".icacheStallCycles")
 173         .desc("Number of cycles fetch is stalled on an Icache miss")
 174         .prereq(icacheStallCycles);
 175
 176     fetchedInsts
 177         .name(name() + ".fetchedInsts")
 178         .desc("Number of instructions fetch has processed")
 179         .prereq(fetchedInsts);
 180
 181     fetchedBranches
 182         .name(name() + ".fetchedBranches")
 183         .desc("Number of fetched branches")
 184         .prereq(fetchedBranches);
 185
 186     predictedBranches
 187         .name(name() + ".predictedBranches")
 188         .desc("Number of branches that fetch has predicted taken")
 189         .prereq(predictedBranches);
 190
 191     fetchCycles
 192         .name(name() + ".fetchCycles")
 193         .desc("Number of cycles fetch has run and was not squashing or"
 194               " blocked")
 195         .prereq(fetchCycles);
 196
 197     fetchIdleCycles
 198         .name(name() + ".fetchIdleCycles")
 199         .desc("Number of cycles fetch was idle")
 200         .prereq(fetchIdleCycles);
 201
 202     fetchSquashCycles
 203         .name(name() + ".fetchSquashCycles")
 204         .desc("Number of cycles fetch has spent squashing")
 205         .prereq(fetchSquashCycles);
 206
 207     fetchBlockedCycles
 208         .name(name() + ".fetchBlockedCycles")
 209         .desc("Number of cycles fetch has spent blocked")
 210         .prereq(fetchBlockedCycles);
 211
 212     fetchedCacheLines
 213         .name(name() + ".fetchedCacheLines")
 214         .desc("Number of cache lines fetched")
 215         .prereq(fetchedCacheLines);
 216
 217     fetchIcacheSquashes
 218         .name(name() + ".fetchIcacheSquashes")
 219         .desc("Number of outstanding Icache misses that were squashed")
 220         .prereq(fetchIcacheSquashes);
 221
 222     fetchNisnDist
 223         .init(/* base value */ 0,
 224               /* last value */ width,
 225               /* bucket size */ 1)
 226         .name(name() + ".rateDist")
 227         .desc("Number of instructions fetched each cycle (Total)")
 228         .flags(Stats::pdf);
 229
 230     idleRate
 231         .name(name() + ".idleRate")
 232         .desc("Percent of cycles fetch was idle")
 233         .prereq(idleRate);
 234     idleRate = fetchIdleCycles * 100 / cpu->numCycles;
 235
 236     branchRate
 237         .name(name() + ".branchRate")
 238         .desc("Number of branch fetches per cycle")
 239         .flags(Stats::total);
 240     branchRate = fetchedBranches / cpu->numCycles;
 241
 242     fetchRate
 243         .name(name() + ".rate")
 244         .desc("Number of inst fetches per cycle")
 245         .flags(Stats::total);
 246     fetchRate = fetchedInsts / cpu->numCycles;
 247
 248     IFQCount
 249         .name(name() + ".IFQ:count")
 250         .desc("cumulative IFQ occupancy")
 251         ;
 252
 253     IFQFcount
 254         .name(name() + ".IFQ:fullCount")
 255         .desc("cumulative IFQ full count")
 256         .flags(Stats::total)
 257         ;
 258
 259     IFQOccupancy
 260         .name(name() + ".IFQ:occupancy")
 261         .desc("avg IFQ occupancy (inst's)")
 262         ;
 263     IFQOccupancy = IFQCount / cpu->numCycles;
 264
 265     IFQLatency
 266         .name(name() + ".IFQ:latency")
 267         .desc("avg IFQ occupant latency (cycle's)")
 268         .flags(Stats::total)
 269         ;
 270
 271     IFQFullRate
 272         .name(name() + ".IFQ:fullRate")
 273         .desc("fraction of time (cycles) IFQ was full")
 274         .flags(Stats::total);
 275         ;
 276     IFQFullRate = IFQFcount * Stats::constant(100) / cpu->numCycles;
 277
 278     dispatchCountStat
 279         .name(name() + ".DIS:count")
 280         .desc("cumulative count of dispatched insts")
 281         .flags(Stats::total)
 282         ;
 283
 284     dispatchedSerializing
 285         .name(name() + ".DIS:serializingInsts")
 286         .desc("count of serializing insts dispatched")
 287         .flags(Stats::total)
 288         ;
 289
 290     dispatchedTempSerializing
 291         .name(name() + ".DIS:tempSerializingInsts")
 292         .desc("count of temporary serializing insts dispatched")
 293         .flags(Stats::total)
 294         ;
 295
 296     dispatchSerializeStallCycles
 297         .name(name() + ".DIS:serializeStallCycles")
 298         .desc("count of cycles dispatch stalled for serializing inst")
 299         .flags(Stats::total)
 300         ;
 301
 302     dispatchRate
 303         .name(name() + ".DIS:rate")
 304         .desc("dispatched insts per cycle")
 305         .flags(Stats::total)
 306         ;
 307     dispatchRate = dispatchCountStat / cpu->numCycles;
 308
 309     regIntFull
 310         .name(name() + ".REG:int:full")
 311         .desc("number of cycles where there were no INT registers")
 312         ;
 313
 314     regFpFull
 315         .name(name() + ".REG:fp:full")
 316         .desc("number of cycles where there were no FP registers")
 317         ;
 318     IFQLatency = IFQOccupancy / dispatchRate;
 319
 320     branchPred.regStats();
 321 }
 322
 323 template <class Impl>
 324 void
 325 FrontEnd<Impl>::tick()
 326 {
 327     if (switchedOut)
 328         return;
 329
 330     for (int insts_to_queue = numInstsReady[-latency];
 331          !instBuffer.empty() && insts_to_queue;
 332          --insts_to_queue)
 333     {
 334         DPRINTF(FE, "Transferring instruction [sn:%lli] to the feBuffer\n",
 335                 instBuffer.front()->seqNum);
 336         feBuffer.push_back(instBuffer.front());
 337         instBuffer.pop_front();
 338     }
 339
 340     numInstsReady.advance();
 341
 342     // @todo: Maybe I want to just have direct communication...
 343     if (fromCommit->doneSeqNum) {
 344         branchPred.update(fromCommit->doneSeqNum, 0);
 345     }
 346
 347     IFQCount += instBufferSize;
 348     IFQFcount += instBufferSize == maxInstBufferSize;
 349
 350     // Fetch cache line
 351     if (status == IcacheAccessComplete) {
 352         cacheBlkValid = true;
 353
 354         status = Running;
 355 //        if (barrierInst)
 356 //            status = SerializeBlocked;
 357         if (freeRegs <= 0)
 358             status = RenameBlocked;
 359         checkBE();
 360     } else if (status == IcacheWaitResponse || status == IcacheWaitRetry) {
 361         DPRINTF(FE, "Still in Icache wait.\n");
 362         icacheStallCycles++;
 363         return;
 364     }
 365
 366     if (status == RenameBlocked || status == SerializeBlocked ||
 367         status == TrapPending || status == BEBlocked) {
 368         // Will cause a one cycle bubble between changing state and
 369         // restarting.
 370         DPRINTF(FE, "In blocked status.\n");
 371
 372         fetchBlockedCycles++;
 373
 374         if (status == SerializeBlocked) {
 375             dispatchSerializeStallCycles++;
 376         }
 377         updateStatus();
 378         return;
 379     } else if (status == QuiescePending) {
 380         DPRINTF(FE, "Waiting for quiesce to execute or get squashed.\n");
 381         return;
 382     } else if (status != IcacheAccessComplete) {
 383         if (fetchCacheLineNextCycle) {
 384             Fault fault = fetchCacheLine();
 385             if (fault != NoFault) {
 386                 handleFault(fault);
 387                 fetchFault = fault;
 388                 return;
 389             }
 390             fetchCacheLineNextCycle = false;
 391         }
 392         // If miss, stall until it returns.
 393         if (status == IcacheWaitResponse || status == IcacheWaitRetry) {
 394             // Tell CPU to not tick me for now.
 395             return;
 396         }
 397     }
 398
 399     fetchCycles++;
 400
 401     int num_inst = 0;
 402
 403     // Otherwise loop and process instructions.
 404     // One way to hack infinite width is to set width and maxInstBufferSize
 405     // both really high.  Inelegant, but probably will work.
 406     while (num_inst < width &&
 407            instBufferSize < maxInstBufferSize) {
 408         // Get instruction from cache line.
 409         DynInstPtr inst = getInstFromCacheline();
 410
 411         if (!inst) {
 412             // PC is no longer in the cache line, end fetch.
 413             // Might want to check this at the end of the cycle so that
 414             // there's no cycle lost to checking for a new cache line.
 415             DPRINTF(FE, "Need to get new cache line\n");
 416             fetchCacheLineNextCycle = true;
 417             break;
 418         }
 419
 420         processInst(inst);
 421
 422         if (status == SerializeBlocked) {
 423             break;
 424         }
 425
 426         // Possibly push into a time buffer that estimates the front end
 427         // latency
 428         instBuffer.push_back(inst);
 429         ++instBufferSize;
 430         numInstsReady[0]++;
 431         ++num_inst;
 432
 433 #if FULL_SYSTEM
 434         if (inst->isQuiesce()) {
 435 //            warn("%lli: Quiesce instruction encountered, halting fetch!", curTick());
 436             status = QuiescePending;
 437             break;
 438         }
 439 #endif
 440
 441         if (inst->predTaken()) {
 442             // Start over with tick?
 443             break;
 444         } else if (freeRegs <= 0) {
 445             DPRINTF(FE, "Ran out of free registers to rename to!\n");
 446             status = RenameBlocked;
 447             break;
 448         } else if (serializeNext) {
 449             break;
 450         }
 451     }
 452
 453     fetchNisnDist.sample(num_inst);
 454     checkBE();
 455
 456     DPRINTF(FE, "Num insts processed: %i, Inst Buffer size: %i, Free "
 457             "Regs %i\n", num_inst, instBufferSize, freeRegs);
 458 }
 459
 460 template <class Impl>
 461 Fault
 462 FrontEnd<Impl>::fetchCacheLine()
 463 {
 464     // Read a cache line, based on the current PC.
 465     Fault fault = NoFault;
 466
 467     //AlphaDep
 468     if (interruptPending && (PC & 0x3)) {
 469         return fault;
 470     }
 471
 472     // Align the fetch PC so it's at the start of a cache block.
 473     Addr fetch_PC = icacheBlockAlignPC(PC);
 474
 475     DPRINTF(FE, "Fetching cache line starting at %#x.\n", fetch_PC);
 476
 477     // Setup the memReq to do a read of the first isntruction's address.
 478     // Set the appropriate read size and flags as well.
 479     memReq = new Request(0, fetch_PC, cacheBlkSize, 0,
 480                          PC, cpu->thread->contextId());
 481
 482     // Translate the instruction request.
 483     fault = cpu->itb->translateAtomic(memReq, thread, false, true);
 484
 485     // Now do the timing access to see whether or not the instruction
 486     // exists within the cache.
 487     if (fault == NoFault) {
 488 #if 0
 489         if (cpu->system->memctrl->badaddr(memReq->paddr) ||
 490             memReq->isUncacheable()) {
 491             DPRINTF(FE, "Fetch: Bad address %#x (hopefully on a "
 492                     "misspeculating path!",
 493                     memReq->paddr);
 494             return TheISA::genMachineCheckFault();
 495         }
 496 #endif
 497
 498         // Build packet here.
 499         PacketPtr data_pkt = new Packet(memReq,
 500                                         Packet::ReadReq, Packet::Broadcast);
 501         data_pkt->dataStatic(cacheData);
 502
 503         if (!icachePort.sendTiming(data_pkt)) {
 504             assert(retryPkt == NULL);
 505             DPRINTF(Fetch, "Out of MSHRs!\n");
 506             status = IcacheWaitRetry;
 507             retryPkt = data_pkt;
 508             cacheBlocked = true;
 509             return NoFault;
 510         }
 511
 512         status = IcacheWaitResponse;
 513     }
 514
 515     // Note that this will set the cache block PC a bit earlier than it should
 516     // be set.
 517     cacheBlkPC = fetch_PC;
 518
 519     ++fetchedCacheLines;
 520
 521     DPRINTF(FE, "Done fetching cache line.\n");
 522
 523     return fault;
 524 }
 525
 526 template <class Impl>
 527 void
 528 FrontEnd<Impl>::processInst(DynInstPtr &inst)
 529 {
 530     if (processBarriers(inst)) {
 531         return;
 532     }
 533
 534     Addr inst_PC = inst->readPC();
 535
 536     if (!inst->isControl()) {
 537         inst->setPredTarg(inst->readNextPC());
 538     } else {
 539         fetchedBranches++;
 540         if (branchPred.predict(inst, inst_PC, inst->threadNumber)) {
 541             predictedBranches++;
 542         }
 543     }
 544
 545     Addr next_PC = inst->readPredTarg();
 546
 547     DPRINTF(FE, "[sn:%lli] Predicted and processed inst PC %#x, next PC "
 548             "%#x\n", inst->seqNum, inst_PC, next_PC);
 549
 550 //    inst->setNextPC(next_PC);
 551
 552     // Not sure where I should set this
 553     PC = next_PC;
 554
 555     renameInst(inst);
 556 }
 557
 558 template <class Impl>
 559 bool
 560 FrontEnd<Impl>::processBarriers(DynInstPtr &inst)
 561 {
 562     if (serializeNext) {
 563         inst->setSerializeBefore();
 564         serializeNext = false;
 565     } else if (!inst->isSerializing() &&
 566                !inst->isIprAccess() &&
 567                !inst->isStoreConditional()) {
 568         return false;
 569     }
 570
 571     if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
 572         !inst->isSerializeHandled()) {
 573         DPRINTF(FE, "Serialize before instruction encountered.\n");
 574
 575         if (!inst->isTempSerializeBefore()) {
 576             dispatchedSerializing++;
 577             inst->setSerializeHandled();
 578         } else {
 579             dispatchedTempSerializing++;
 580         }
 581
 582         // Change status over to SerializeBlocked so that other stages know
 583         // what this is blocked on.
 584 //        status = SerializeBlocked;
 585
 586 //        barrierInst = inst;
 587 //        return true;
 588     } else if ((inst->isStoreConditional() || inst->isSerializeAfter())
 589                && !inst->isSerializeHandled()) {
 590         DPRINTF(FE, "Serialize after instruction encountered.\n");
 591
 592         inst->setSerializeHandled();
 593
 594         dispatchedSerializing++;
 595
 596         serializeNext = true;
 597         return false;
 598     }
 599     return false;
 600 }
 601
 602 template <class Impl>
 603 void
 604 FrontEnd<Impl>::handleFault(Fault &fault)
 605 {
 606     DPRINTF(FE, "Fault at fetch, telling commit\n");
 607
 608     // We're blocked on the back end until it handles this fault.
 609     status = TrapPending;
 610
 611     // Get a sequence number.
 612     InstSeqNum inst_seq = getAndIncrementInstSeq();
 613     // We will use a nop in order to carry the fault.
 614     ExtMachInst ext_inst = TheISA::NoopMachInst;
 615
 616     // Create a new DynInst from the dummy nop.
 617     DynInstPtr instruction = new DynInst(ext_inst, PC,
 618                                          PC+sizeof(MachInst),
 619                                          inst_seq, cpu);
 620     instruction->setPredTarg(instruction->readNextPC());
 621 //    instruction->setThread(tid);
 622
 623 //    instruction->setASID(tid);
 624
 625     instruction->setThreadState(thread);
 626
 627     instruction->traceData = NULL;
 628
 629     instruction->fault = fault;
 630     instruction->setCanIssue();
 631     instBuffer.push_back(instruction);
 632     numInstsReady[0]++;
 633     ++instBufferSize;
 634 }
 635
 636 template <class Impl>
 637 void
 638 FrontEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC,
 639                        const bool is_branch, const bool branch_taken)
 640 {
 641     DPRINTF(FE, "Squashing from [sn:%lli], setting PC to %#x\n",
 642             squash_num, next_PC);
 643
 644     if (fetchFault != NoFault)
 645         fetchFault = NoFault;
 646
 647     while (!instBuffer.empty() &&
 648            instBuffer.back()->seqNum > squash_num) {
 649         DynInstPtr inst = instBuffer.back();
 650
 651         DPRINTF(FE, "Squashing instruction [sn:%lli] PC %#x\n",
 652                 inst->seqNum, inst->readPC());
 653
 654         inst->clearDependents();
 655
 656         instBuffer.pop_back();
 657         --instBufferSize;
 658
 659         freeRegs+= inst->numDestRegs();
 660     }
 661
 662     while (!feBuffer.empty() &&
 663            feBuffer.back()->seqNum > squash_num) {
 664         DynInstPtr inst = feBuffer.back();
 665
 666         DPRINTF(FE, "Squashing instruction [sn:%lli] PC %#x\n",
 667                 inst->seqNum, inst->readPC());
 668
 669         inst->clearDependents();
 670
 671         feBuffer.pop_back();
 672         --instBufferSize;
 673
 674         freeRegs+= inst->numDestRegs();
 675     }
 676
 677     // Copy over rename table from the back end.
 678     renameTable.copyFrom(backEnd->renameTable);
 679
 680     PC = next_PC;
 681
 682     // Update BP with proper information.
 683     if (is_branch) {
 684         branchPred.squash(squash_num, next_PC, branch_taken, 0);
 685     } else {
 686         branchPred.squash(squash_num, 0);
 687     }
 688
 689     // Clear the icache miss if it's outstanding.
 690     if (status == IcacheWaitResponse) {
 691         DPRINTF(FE, "Squashing outstanding Icache access.\n");
 692         memReq = NULL;
 693     }
 694 /*
 695     if (status == SerializeBlocked) {
 696         assert(barrierInst->seqNum > squash_num);
 697         barrierInst = NULL;
 698     }
 699 */
 700     // Unless this squash originated from the front end, we're probably
 701     // in running mode now.
 702     // Actually might want to make this latency dependent.
 703     status = Running;
 704     fetchCacheLineNextCycle = true;
 705 }
 706
 707 template <class Impl>
 708 typename Impl::DynInstPtr
 709 FrontEnd<Impl>::getInst()
 710 {
 711     if (feBuffer.empty()) {
 712         return NULL;
 713     }
 714
 715     DynInstPtr inst = feBuffer.front();
 716
 717     if (inst->isSerializeBefore() || inst->isIprAccess()) {
 718         DPRINTF(FE, "Back end is getting a serialize before inst\n");
 719         if (!backEnd->robEmpty()) {
 720             DPRINTF(FE, "Rob is not empty yet, not returning inst\n");
 721             return NULL;
 722         }
 723         inst->clearSerializeBefore();
 724     }
 725
 726     feBuffer.pop_front();
 727
 728     --instBufferSize;
 729
 730     dispatchCountStat++;
 731
 732     return inst;
 733 }
 734
 735 template <class Impl>
 736 void
 737 FrontEnd<Impl>::processCacheCompletion(PacketPtr pkt)
 738 {
 739     DPRINTF(FE, "Processing cache completion\n");
 740
 741     // Do something here.
 742     if (status != IcacheWaitResponse ||
 743         pkt->req != memReq ||
 744         switchedOut) {
 745         DPRINTF(FE, "Previous fetch was squashed.\n");
 746         fetchIcacheSquashes++;
 747         delete pkt->req;
 748         delete pkt;
 749         return;
 750     }
 751
 752     status = IcacheAccessComplete;
 753
 754 /*    if (checkStall(tid)) {
 755         fetchStatus[tid] = Blocked;
 756     } else {
 757         fetchStatus[tid] = IcacheMissComplete;
 758     }
 759 */
 760 //    memcpy(cacheData, memReq->data, memReq->size);
 761
 762     // Reset the completion event to NULL.
 763 //    memReq->completionEvent = NULL;
 764     delete pkt->req;
 765     delete pkt;
 766     memReq = NULL;
 767 }
 768
 769 template <class Impl>
 770 void
 771 FrontEnd<Impl>::addFreeRegs(int num_freed)
 772 {
 773     if (status == RenameBlocked && freeRegs + num_freed > 0) {
 774         status = Running;
 775     }
 776
 777     DPRINTF(FE, "Adding %i freed registers\n", num_freed);
 778
 779     freeRegs+= num_freed;
 780
 781 //    assert(freeRegs <= numPhysRegs);
 782     if (freeRegs > numPhysRegs)
 783         freeRegs = numPhysRegs;
 784 }
 785
 786 template <class Impl>
 787 void
 788 FrontEnd<Impl>::recvRetry()
 789 {
 790     assert(cacheBlocked);
 791     if (retryPkt != NULL) {
 792         assert(status == IcacheWaitRetry);
 793
 794         if (icachePort.sendTiming(retryPkt)) {
 795             status = IcacheWaitResponse;
 796             retryPkt = NULL;
 797             cacheBlocked = false;
 798         }
 799     } else {
 800         // Access has been squashed since it was sent out.  Just clear
 801         // the cache being blocked.
 802         cacheBlocked = false;
 803     }
 804
 805 }
 806
 807 template <class Impl>
 808 bool
 809 FrontEnd<Impl>::updateStatus()
 810 {
 811     bool serialize_block = !backEnd->robEmpty() || instBufferSize;
 812     bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
 813     bool ret_val = false;
 814
 815     if (status == SerializeBlocked && !serialize_block) {
 816         status = SerializeComplete;
 817         ret_val = true;
 818     }
 819
 820     if (status == BEBlocked && !be_block) {
 821 //        if (barrierInst) {
 822 //            status = SerializeBlocked;
 823 //        } else {
 824             status = Running;
 825 //        }
 826         ret_val = true;
 827     }
 828     return ret_val;
 829 }
 830
 831 template <class Impl>
 832 void
 833 FrontEnd<Impl>::checkBE()
 834 {
 835     bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
 836     if (be_block) {
 837         if (status == Running || status == Idle) {
 838             status = BEBlocked;
 839         }
 840     }
 841 }
 842
 843 template <class Impl>
 844 typename Impl::DynInstPtr
 845 FrontEnd<Impl>::getInstFromCacheline()
 846 {
 847 /*
 848     if (status == SerializeComplete) {
 849         DynInstPtr inst = barrierInst;
 850         status = Running;
 851         barrierInst = NULL;
 852         inst->clearSerializeBefore();
 853         return inst;
 854     }
 855 */
 856     InstSeqNum inst_seq;
 857     MachInst inst;
 858     // @todo: Fix this magic number used here to handle word offset (and
 859     // getting rid of PAL bit)
 860     unsigned offset = (PC & cacheBlkMask) & ~3;
 861
 862     // PC of inst is not in this cache block
 863     if (PC >= (cacheBlkPC + cacheBlkSize) || PC < cacheBlkPC || !cacheBlkValid) {
 864         return NULL;
 865     }
 866
 867     //////////////////////////
 868     // Fetch one instruction
 869     //////////////////////////
 870
 871     // Get a sequence number.
 872     inst_seq = getAndIncrementInstSeq();
 873
 874     // Make sure this is a valid index.
 875     assert(offset <= cacheBlkSize - sizeof(MachInst));
 876
 877     // Get the instruction from the array of the cache line.
 878     inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
 879
 880 #if THE_ISA == ALPHA_ISA
 881     ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC);
 882 #elif THE_ISA == SPARC_ISA
 883     ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc);
 884 #endif
 885
 886     // Create a new DynInst from the instruction fetched.
 887     DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
 888                                          inst_seq, cpu);
 889
 890     instruction->setThreadState(thread);
 891
 892     DPRINTF(FE, "Instruction [sn:%lli] created, with PC %#x\n%s\n",
 893             inst_seq, instruction->readPC(),
 894             instruction->staticInst->disassemble(PC));
 895
 896     instruction->traceData =
 897         Trace::getInstRecord(curTick(), tc,
 898                              instruction->staticInst,
 899                              instruction->readPC());
 900
 901     // Increment stat of fetched instructions.
 902     ++fetchedInsts;
 903
 904     return instruction;
 905 }
 906
 907 template <class Impl>
 908 void
 909 FrontEnd<Impl>::renameInst(DynInstPtr &inst)
 910 {
 911     DynInstPtr src_inst = NULL;
 912     int num_src_regs = inst->numSrcRegs();
 913     if (num_src_regs == 0) {
 914         inst->setCanIssue();
 915     } else {
 916         for (int i = 0; i < num_src_regs; ++i) {
 917             src_inst = renameTable[inst->srcRegIdx(i)];
 918
 919             inst->setSrcInst(src_inst, i);
 920
 921             DPRINTF(FE, "[sn:%lli]: Src reg %i is inst [sn:%lli]\n",
 922                     inst->seqNum, (int)inst->srcRegIdx(i), src_inst->seqNum);
 923
 924             if (src_inst->isResultReady()) {
 925                 DPRINTF(FE, "Reg ready.\n");
 926                 inst->markSrcRegReady(i);
 927             } else {
 928                 DPRINTF(FE, "Adding to dependent list.\n");
 929                 src_inst->addDependent(inst);
 930             }
 931         }
 932     }
 933
 934     for (int i = 0; i < inst->numDestRegs(); ++i) {
 935         RegIndex idx = inst->destRegIdx(i);
 936
 937         DPRINTF(FE, "Dest reg %i is now inst [sn:%lli], was previously "
 938                 "[sn:%lli]\n",
 939                 (int)inst->destRegIdx(i), inst->seqNum,
 940                 renameTable[idx]->seqNum);
 941
 942         inst->setPrevDestInst(renameTable[idx], i);
 943
 944         renameTable[idx] = inst;
 945         --freeRegs;
 946     }
 947 }
 948
 949 template <class Impl>
 950 void
 951 FrontEnd<Impl>::wakeFromQuiesce()
 952 {
 953     DPRINTF(FE, "Waking up from quiesce\n");
 954     // Hopefully this is safe
 955     status = Running;
 956 }
 957
 958 template <class Impl>
 959 void
 960 FrontEnd<Impl>::switchOut()
 961 {
 962     switchedOut = true;
 963     cpu->signalSwitched();
 964 }
 965
 966 template <class Impl>
 967 void
 968 FrontEnd<Impl>::doSwitchOut()
 969 {
 970     memReq = NULL;
 971     squash(0, 0);
 972     instBuffer.clear();
 973     instBufferSize = 0;
 974     feBuffer.clear();
 975     status = Idle;
 976 }
 977
 978 template <class Impl>
 979 void
 980 FrontEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
 981 {
 982     assert(freeRegs == numPhysRegs);
 983     fetchCacheLineNextCycle = true;
 984
 985     cacheBlkValid = false;
 986
 987 #if !FULL_SYSTEM
 988 //    pTable = params->pTable;
 989 #endif
 990     fetchFault = NoFault;
 991     serializeNext = false;
 992     barrierInst = NULL;
 993     status = Running;
 994     switchedOut = false;
 995     interruptPending = false;
 996 }
 997
 998 template <class Impl>
 999 void
1000 FrontEnd<Impl>::dumpInsts()
1001 {
1002     cprintf("instBuffer size: %i\n", instBuffer.size());
1003
1004     InstBuffIt buff_it = instBuffer.begin();
1005
1006     for (int num = 0; buff_it != instBuffer.end(); num++) {
1007         cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1008                 "Squashed:%i\n\n",
1009                 num, (*buff_it)->readPC(), (*buff_it)->threadNumber,
1010                 (*buff_it)->seqNum, (*buff_it)->isIssued(),
1011                 (*buff_it)->isSquashed());
1012         buff_it++;
1013     }
1014 }