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31 #include "config/use_checker.hh"
33 #include "arch/faults.hh"
34 #include "arch/isa_traits.hh"
35 #include "base/statistics.hh"
36 #include "cpu/thread_context.hh"
37 #include "cpu/exetrace.hh"
38 #include "cpu/ozone/front_end.hh"
39 #include "mem/mem_object.hh"
40 #include "mem/packet.hh"
41 #include "mem/request.hh"
44 #include "cpu/checker/cpu.hh"
47 using namespace TheISA;
51 FrontEnd<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
53 panic("FrontEnd doesn't expect recvAtomic callback!");
59 FrontEnd<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
61 panic("FrontEnd doesn't expect recvFunctional callback!");
66 FrontEnd<Impl>::IcachePort::recvStatusChange(Status status)
68 if (status == RangeChange)
71 panic("FrontEnd doesn't expect recvStatusChange callback!");
76 FrontEnd<Impl>::IcachePort::recvTiming(Packet *pkt)
78 fe->processCacheCompletion(pkt);
84 FrontEnd<Impl>::IcachePort::recvRetry()
90 FrontEnd<Impl>::FrontEnd(Params *params)
95 maxInstBufferSize(params->maxInstBufferSize),
96 width(params->frontEndWidth),
97 freeRegs(params->numPhysicalRegs),
98 numPhysRegs(params->numPhysicalRegs),
100 interruptPending(false)
107 // Size of cache block.
110 assert(isPowerOf2(cacheBlkSize));
112 // Create mask to get rid of offset bits.
113 cacheBlkMask = (cacheBlkSize - 1);
115 // Create space to store a cache line.
116 cacheData = new uint8_t[cacheBlkSize];
118 fetchCacheLineNextCycle = true;
120 cacheBlkValid = cacheBlocked = false;
124 fetchFault = NoFault;
127 template <class Impl>
129 FrontEnd<Impl>::name() const
131 return cpu->name() + ".frontend";
134 template <class Impl>
136 FrontEnd<Impl>::setCPU(CPUType *cpu_ptr)
140 icachePort.setName(this->name() + "-iport");
144 cpu->checker->setIcachePort(&icachePort);
149 template <class Impl>
151 FrontEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
154 // @todo: Hardcoded for now. Allow this to be set by a latency.
155 fromCommit = comm->getWire(-1);
158 template <class Impl>
160 FrontEnd<Impl>::setTC(ThreadContext *tc_ptr)
165 template <class Impl>
167 FrontEnd<Impl>::regStats()
170 .name(name() + ".icacheStallCycles")
171 .desc("Number of cycles fetch is stalled on an Icache miss")
172 .prereq(icacheStallCycles);
175 .name(name() + ".fetchedInsts")
176 .desc("Number of instructions fetch has processed")
177 .prereq(fetchedInsts);
180 .name(name() + ".fetchedBranches")
181 .desc("Number of fetched branches")
182 .prereq(fetchedBranches);
185 .name(name() + ".predictedBranches")
186 .desc("Number of branches that fetch has predicted taken")
187 .prereq(predictedBranches);
190 .name(name() + ".fetchCycles")
191 .desc("Number of cycles fetch has run and was not squashing or"
193 .prereq(fetchCycles);
196 .name(name() + ".fetchIdleCycles")
197 .desc("Number of cycles fetch was idle")
198 .prereq(fetchIdleCycles);
201 .name(name() + ".fetchSquashCycles")
202 .desc("Number of cycles fetch has spent squashing")
203 .prereq(fetchSquashCycles);
206 .name(name() + ".fetchBlockedCycles")
207 .desc("Number of cycles fetch has spent blocked")
208 .prereq(fetchBlockedCycles);
211 .name(name() + ".fetchedCacheLines")
212 .desc("Number of cache lines fetched")
213 .prereq(fetchedCacheLines);
216 .name(name() + ".fetchIcacheSquashes")
217 .desc("Number of outstanding Icache misses that were squashed")
218 .prereq(fetchIcacheSquashes);
221 .init(/* base value */ 0,
222 /* last value */ width,
224 .name(name() + ".rateDist")
225 .desc("Number of instructions fetched each cycle (Total)")
229 .name(name() + ".idleRate")
230 .desc("Percent of cycles fetch was idle")
232 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
235 .name(name() + ".branchRate")
236 .desc("Number of branch fetches per cycle")
237 .flags(Stats::total);
238 branchRate = fetchedBranches / cpu->numCycles;
241 .name(name() + ".rate")
242 .desc("Number of inst fetches per cycle")
243 .flags(Stats::total);
244 fetchRate = fetchedInsts / cpu->numCycles;
247 .name(name() + ".IFQ:count")
248 .desc("cumulative IFQ occupancy")
252 .name(name() + ".IFQ:fullCount")
253 .desc("cumulative IFQ full count")
258 .name(name() + ".IFQ:occupancy")
259 .desc("avg IFQ occupancy (inst's)")
261 IFQOccupancy = IFQCount / cpu->numCycles;
264 .name(name() + ".IFQ:latency")
265 .desc("avg IFQ occupant latency (cycle's)")
270 .name(name() + ".IFQ:fullRate")
271 .desc("fraction of time (cycles) IFQ was full")
272 .flags(Stats::total);
274 IFQFullRate = IFQFcount * Stats::constant(100) / cpu->numCycles;
277 .name(name() + ".DIS:count")
278 .desc("cumulative count of dispatched insts")
282 dispatchedSerializing
283 .name(name() + ".DIS:serializingInsts")
284 .desc("count of serializing insts dispatched")
288 dispatchedTempSerializing
289 .name(name() + ".DIS:tempSerializingInsts")
290 .desc("count of temporary serializing insts dispatched")
294 dispatchSerializeStallCycles
295 .name(name() + ".DIS:serializeStallCycles")
296 .desc("count of cycles dispatch stalled for serializing inst")
301 .name(name() + ".DIS:rate")
302 .desc("dispatched insts per cycle")
305 dispatchRate = dispatchCountStat / cpu->numCycles;
308 .name(name() + ".REG:int:full")
309 .desc("number of cycles where there were no INT registers")
313 .name(name() + ".REG:fp:full")
314 .desc("number of cycles where there were no FP registers")
316 IFQLatency = IFQOccupancy / dispatchRate;
318 branchPred.regStats();
321 template <class Impl>
323 FrontEnd<Impl>::tick()
328 // @todo: Maybe I want to just have direct communication...
329 if (fromCommit->doneSeqNum) {
330 branchPred.update(fromCommit->doneSeqNum, 0);
333 IFQCount += instBufferSize;
334 IFQFcount += instBufferSize == maxInstBufferSize;
337 if (status == IcacheAccessComplete) {
338 cacheBlkValid = true;
342 status = SerializeBlocked;
344 status = RenameBlocked;
346 } else if (status == IcacheWaitResponse || status == IcacheWaitRetry) {
347 DPRINTF(FE, "Still in Icache wait.\n");
352 if (status == RenameBlocked || status == SerializeBlocked ||
353 status == TrapPending || status == BEBlocked) {
354 // Will cause a one cycle bubble between changing state and
356 DPRINTF(FE, "In blocked status.\n");
358 fetchBlockedCycles++;
360 if (status == SerializeBlocked) {
361 dispatchSerializeStallCycles++;
365 } else if (status == QuiescePending) {
366 DPRINTF(FE, "Waiting for quiesce to execute or get squashed.\n");
368 } else if (status != IcacheAccessComplete) {
369 if (fetchCacheLineNextCycle) {
370 Fault fault = fetchCacheLine();
371 if (fault != NoFault) {
376 fetchCacheLineNextCycle = false;
378 // If miss, stall until it returns.
379 if (status == IcacheWaitResponse || status == IcacheWaitRetry) {
380 // Tell CPU to not tick me for now.
389 // Otherwise loop and process instructions.
390 // One way to hack infinite width is to set width and maxInstBufferSize
391 // both really high. Inelegant, but probably will work.
392 while (num_inst < width &&
393 instBufferSize < maxInstBufferSize) {
394 // Get instruction from cache line.
395 DynInstPtr inst = getInstFromCacheline();
398 // PC is no longer in the cache line, end fetch.
399 // Might want to check this at the end of the cycle so that
400 // there's no cycle lost to checking for a new cache line.
401 DPRINTF(FE, "Need to get new cache line\n");
402 fetchCacheLineNextCycle = true;
408 if (status == SerializeBlocked) {
412 // Possibly push into a time buffer that estimates the front end
414 instBuffer.push_back(inst);
419 if (inst->isQuiesce()) {
420 warn("%lli: Quiesce instruction encountered, halting fetch!", curTick);
421 status = QuiescePending;
426 if (inst->predTaken()) {
427 // Start over with tick?
429 } else if (freeRegs <= 0) {
430 DPRINTF(FE, "Ran out of free registers to rename to!\n");
431 status = RenameBlocked;
433 } else if (serializeNext) {
438 fetchNisnDist.sample(num_inst);
441 DPRINTF(FE, "Num insts processed: %i, Inst Buffer size: %i, Free "
442 "Regs %i\n", num_inst, instBufferSize, freeRegs);
445 template <class Impl>
447 FrontEnd<Impl>::fetchCacheLine()
449 // Read a cache line, based on the current PC.
451 // Flag to say whether or not address is physical addr.
452 unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
455 #endif // FULL_SYSTEM
456 Fault fault = NoFault;
458 if (interruptPending && flags == 0) {
462 // Align the fetch PC so it's at the start of a cache block.
463 Addr fetch_PC = icacheBlockAlignPC(PC);
465 DPRINTF(FE, "Fetching cache line starting at %#x.\n", fetch_PC);
467 // Setup the memReq to do a read of the first isntruction's address.
468 // Set the appropriate read size and flags as well.
469 memReq = new Request(0, fetch_PC, cacheBlkSize, flags,
470 fetch_PC, cpu->readCpuId(), 0);
472 // Translate the instruction request.
473 fault = cpu->translateInstReq(memReq, thread);
475 // Now do the timing access to see whether or not the instruction
476 // exists within the cache.
477 if (fault == NoFault) {
479 if (cpu->system->memctrl->badaddr(memReq->paddr) ||
480 memReq->flags & UNCACHEABLE) {
481 DPRINTF(FE, "Fetch: Bad address %#x (hopefully on a "
482 "misspeculating path!",
484 return TheISA::genMachineCheckFault();
488 // Build packet here.
489 PacketPtr data_pkt = new Packet(memReq,
490 Packet::ReadReq, Packet::Broadcast);
491 data_pkt->dataStatic(cacheData);
493 if (!icachePort.sendTiming(data_pkt)) {
494 assert(retryPkt == NULL);
495 DPRINTF(Fetch, "Out of MSHRs!\n");
496 status = IcacheWaitRetry;
502 status = IcacheWaitResponse;
505 // Note that this will set the cache block PC a bit earlier than it should
507 cacheBlkPC = fetch_PC;
511 DPRINTF(FE, "Done fetching cache line.\n");
516 template <class Impl>
518 FrontEnd<Impl>::processInst(DynInstPtr &inst)
520 if (processBarriers(inst)) {
524 Addr inst_PC = inst->readPC();
526 if (!inst->isControl()) {
527 inst->setPredTarg(inst->readNextPC());
530 if (branchPred.predict(inst, inst_PC, inst->threadNumber)) {
535 Addr next_PC = inst->readPredTarg();
537 DPRINTF(FE, "[sn:%lli] Predicted and processed inst PC %#x, next PC "
538 "%#x\n", inst->seqNum, inst_PC, next_PC);
540 // inst->setNextPC(next_PC);
542 // Not sure where I should set this
548 template <class Impl>
550 FrontEnd<Impl>::processBarriers(DynInstPtr &inst)
553 inst->setSerializeBefore();
554 serializeNext = false;
555 } else if (!inst->isSerializing() &&
556 !inst->isIprAccess() &&
557 !inst->isStoreConditional()) {
561 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
562 !inst->isSerializeHandled()) {
563 DPRINTF(FE, "Serialize before instruction encountered.\n");
565 if (!inst->isTempSerializeBefore()) {
566 dispatchedSerializing++;
567 inst->setSerializeHandled();
569 dispatchedTempSerializing++;
572 // Change status over to SerializeBlocked so that other stages know
573 // what this is blocked on.
574 status = SerializeBlocked;
578 } else if ((inst->isStoreConditional() || inst->isSerializeAfter())
579 && !inst->isSerializeHandled()) {
580 DPRINTF(FE, "Serialize after instruction encountered.\n");
582 inst->setSerializeHandled();
584 dispatchedSerializing++;
586 serializeNext = true;
592 template <class Impl>
594 FrontEnd<Impl>::handleFault(Fault &fault)
596 DPRINTF(FE, "Fault at fetch, telling commit\n");
598 // We're blocked on the back end until it handles this fault.
599 status = TrapPending;
601 // Get a sequence number.
602 InstSeqNum inst_seq = getAndIncrementInstSeq();
603 // We will use a nop in order to carry the fault.
604 ExtMachInst ext_inst = TheISA::NoopMachInst;
606 // Create a new DynInst from the dummy nop.
607 DynInstPtr instruction = new DynInst(ext_inst, PC,
610 instruction->setPredTarg(instruction->readNextPC());
611 // instruction->setThread(tid);
613 // instruction->setASID(tid);
615 instruction->setThreadState(thread);
617 instruction->traceData = NULL;
619 instruction->fault = fault;
620 instruction->setCanIssue();
621 instBuffer.push_back(instruction);
625 template <class Impl>
627 FrontEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC,
628 const bool is_branch, const bool branch_taken)
630 DPRINTF(FE, "Squashing from [sn:%lli], setting PC to %#x\n",
631 squash_num, next_PC);
633 if (fetchFault != NoFault)
634 fetchFault = NoFault;
636 while (!instBuffer.empty() &&
637 instBuffer.back()->seqNum > squash_num) {
638 DynInstPtr inst = instBuffer.back();
640 DPRINTF(FE, "Squashing instruction [sn:%lli] PC %#x\n",
641 inst->seqNum, inst->readPC());
643 inst->clearDependents();
645 instBuffer.pop_back();
648 freeRegs+= inst->numDestRegs();
651 // Copy over rename table from the back end.
652 renameTable.copyFrom(backEnd->renameTable);
656 // Update BP with proper information.
658 branchPred.squash(squash_num, next_PC, branch_taken, 0);
660 branchPred.squash(squash_num, 0);
663 // Clear the icache miss if it's outstanding.
664 if (status == IcacheWaitResponse) {
665 DPRINTF(FE, "Squashing outstanding Icache access.\n");
669 if (status == SerializeBlocked) {
670 assert(barrierInst->seqNum > squash_num);
674 // Unless this squash originated from the front end, we're probably
675 // in running mode now.
676 // Actually might want to make this latency dependent.
678 fetchCacheLineNextCycle = true;
681 template <class Impl>
682 typename Impl::DynInstPtr
683 FrontEnd<Impl>::getInst()
685 if (instBufferSize == 0) {
689 DynInstPtr inst = instBuffer.front();
691 instBuffer.pop_front();
700 template <class Impl>
702 FrontEnd<Impl>::processCacheCompletion(PacketPtr pkt)
704 DPRINTF(FE, "Processing cache completion\n");
706 // Do something here.
707 if (status != IcacheWaitResponse ||
708 pkt->req != memReq ||
710 DPRINTF(FE, "Previous fetch was squashed.\n");
711 fetchIcacheSquashes++;
717 status = IcacheAccessComplete;
719 /* if (checkStall(tid)) {
720 fetchStatus[tid] = Blocked;
722 fetchStatus[tid] = IcacheMissComplete;
725 // memcpy(cacheData, memReq->data, memReq->size);
727 // Reset the completion event to NULL.
728 // memReq->completionEvent = NULL;
734 template <class Impl>
736 FrontEnd<Impl>::addFreeRegs(int num_freed)
738 if (status == RenameBlocked && freeRegs + num_freed > 0) {
742 DPRINTF(FE, "Adding %i freed registers\n", num_freed);
744 freeRegs+= num_freed;
746 // assert(freeRegs <= numPhysRegs);
747 if (freeRegs > numPhysRegs)
748 freeRegs = numPhysRegs;
751 template <class Impl>
753 FrontEnd<Impl>::recvRetry()
755 assert(cacheBlocked);
756 if (retryPkt != NULL) {
757 assert(status == IcacheWaitRetry);
759 if (icachePort.sendTiming(retryPkt)) {
760 status = IcacheWaitResponse;
762 cacheBlocked = false;
765 // Access has been squashed since it was sent out. Just clear
766 // the cache being blocked.
767 cacheBlocked = false;
772 template <class Impl>
774 FrontEnd<Impl>::updateStatus()
776 bool serialize_block = !backEnd->robEmpty() || instBufferSize;
777 bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
778 bool ret_val = false;
780 if (status == SerializeBlocked && !serialize_block) {
781 status = SerializeComplete;
785 if (status == BEBlocked && !be_block) {
787 status = SerializeBlocked;
796 template <class Impl>
798 FrontEnd<Impl>::checkBE()
800 bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
802 if (status == Running || status == Idle) {
808 template <class Impl>
809 typename Impl::DynInstPtr
810 FrontEnd<Impl>::getInstFromCacheline()
812 if (status == SerializeComplete) {
813 DynInstPtr inst = barrierInst;
816 inst->clearSerializeBefore();
822 // @todo: Fix this magic number used here to handle word offset (and
823 // getting rid of PAL bit)
824 unsigned offset = (PC & cacheBlkMask) & ~3;
826 // PC of inst is not in this cache block
827 if (PC >= (cacheBlkPC + cacheBlkSize) || PC < cacheBlkPC || !cacheBlkValid) {
831 //////////////////////////
832 // Fetch one instruction
833 //////////////////////////
835 // Get a sequence number.
836 inst_seq = getAndIncrementInstSeq();
838 // Make sure this is a valid index.
839 assert(offset <= cacheBlkSize - sizeof(MachInst));
841 // Get the instruction from the array of the cache line.
842 inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
844 ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC);
846 // Create a new DynInst from the instruction fetched.
847 DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
850 instruction->setThreadState(thread);
852 DPRINTF(FE, "Instruction [sn:%lli] created, with PC %#x\n%s\n",
853 inst_seq, instruction->readPC(),
854 instruction->staticInst->disassemble(PC));
856 instruction->traceData =
857 Trace::getInstRecord(curTick, tc, cpu,
858 instruction->staticInst,
859 instruction->readPC(), 0);
861 // Increment stat of fetched instructions.
867 template <class Impl>
869 FrontEnd<Impl>::renameInst(DynInstPtr &inst)
871 DynInstPtr src_inst = NULL;
872 int num_src_regs = inst->numSrcRegs();
873 if (num_src_regs == 0) {
876 for (int i = 0; i < num_src_regs; ++i) {
877 src_inst = renameTable[inst->srcRegIdx(i)];
879 inst->setSrcInst(src_inst, i);
881 DPRINTF(FE, "[sn:%lli]: Src reg %i is inst [sn:%lli]\n",
882 inst->seqNum, (int)inst->srcRegIdx(i), src_inst->seqNum);
884 if (src_inst->isResultReady()) {
885 DPRINTF(FE, "Reg ready.\n");
886 inst->markSrcRegReady(i);
888 DPRINTF(FE, "Adding to dependent list.\n");
889 src_inst->addDependent(inst);
894 for (int i = 0; i < inst->numDestRegs(); ++i) {
895 RegIndex idx = inst->destRegIdx(i);
897 DPRINTF(FE, "Dest reg %i is now inst [sn:%lli], was previously "
899 (int)inst->destRegIdx(i), inst->seqNum,
900 renameTable[idx]->seqNum);
902 inst->setPrevDestInst(renameTable[idx], i);
904 renameTable[idx] = inst;
909 template <class Impl>
911 FrontEnd<Impl>::wakeFromQuiesce()
913 DPRINTF(FE, "Waking up from quiesce\n");
914 // Hopefully this is safe
918 template <class Impl>
920 FrontEnd<Impl>::switchOut()
923 cpu->signalSwitched();
926 template <class Impl>
928 FrontEnd<Impl>::doSwitchOut()
937 template <class Impl>
939 FrontEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
941 assert(freeRegs == numPhysRegs);
942 fetchCacheLineNextCycle = true;
944 cacheBlkValid = false;
947 // pTable = params->pTable;
949 fetchFault = NoFault;
950 serializeNext = false;
954 interruptPending = false;
957 template <class Impl>
959 FrontEnd<Impl>::dumpInsts()
961 cprintf("instBuffer size: %i\n", instBuffer.size());
963 InstBuffIt buff_it = instBuffer.begin();
965 for (int num = 0; buff_it != instBuffer.end(); num++) {
966 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
968 num, (*buff_it)->readPC(), (*buff_it)->threadNumber,
969 (*buff_it)->seqNum, (*buff_it)->isIssued(),
970 (*buff_it)->isSquashed());