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31 #include "config/use_checker.hh"
33 #include "arch/faults.hh"
34 #include "arch/isa_traits.hh"
35 #include "base/statistics.hh"
36 #include "cpu/thread_context.hh"
37 #include "cpu/exetrace.hh"
38 #include "cpu/ozone/front_end.hh"
39 #include "mem/packet.hh"
40 #include "mem/request.hh"
43 #include "cpu/checker/cpu.hh"
46 using namespace TheISA;
50 FrontEnd<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
52 panic("FrontEnd doesn't expect recvAtomic callback!");
58 FrontEnd<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
60 panic("FrontEnd doesn't expect recvFunctional callback!");
65 FrontEnd<Impl>::IcachePort::recvStatusChange(Status status)
67 if (status == RangeChange)
70 panic("FrontEnd doesn't expect recvStatusChange callback!");
75 FrontEnd<Impl>::IcachePort::recvTiming(Packet *pkt)
77 fe->processCacheCompletion(pkt);
83 FrontEnd<Impl>::IcachePort::recvRetry()
89 FrontEnd<Impl>::FrontEnd(Params *params)
94 maxInstBufferSize(params->maxInstBufferSize),
95 width(params->frontEndWidth),
96 freeRegs(params->numPhysicalRegs),
97 numPhysRegs(params->numPhysicalRegs),
99 interruptPending(false)
106 // Size of cache block.
109 assert(isPowerOf2(cacheBlkSize));
111 // Create mask to get rid of offset bits.
112 cacheBlkMask = (cacheBlkSize - 1);
114 // Create space to store a cache line.
115 cacheData = new uint8_t[cacheBlkSize];
117 fetchCacheLineNextCycle = true;
119 cacheBlkValid = cacheBlocked = false;
123 fetchFault = NoFault;
126 template <class Impl>
128 FrontEnd<Impl>::name() const
130 return cpu->name() + ".frontend";
133 template <class Impl>
135 FrontEnd<Impl>::setCPU(CPUType *cpu_ptr)
139 icachePort.setName(this->name() + "-iport");
141 Port *mem_dport = mem->getPort("");
142 icachePort.setPeer(mem_dport);
143 mem_dport->setPeer(&icachePort);
147 cpu->checker->setIcachePort(&icachePort);
152 template <class Impl>
154 FrontEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
157 // @todo: Hardcoded for now. Allow this to be set by a latency.
158 fromCommit = comm->getWire(-1);
161 template <class Impl>
163 FrontEnd<Impl>::setTC(ThreadContext *tc_ptr)
168 template <class Impl>
170 FrontEnd<Impl>::regStats()
173 .name(name() + ".icacheStallCycles")
174 .desc("Number of cycles fetch is stalled on an Icache miss")
175 .prereq(icacheStallCycles);
178 .name(name() + ".fetchedInsts")
179 .desc("Number of instructions fetch has processed")
180 .prereq(fetchedInsts);
183 .name(name() + ".fetchedBranches")
184 .desc("Number of fetched branches")
185 .prereq(fetchedBranches);
188 .name(name() + ".predictedBranches")
189 .desc("Number of branches that fetch has predicted taken")
190 .prereq(predictedBranches);
193 .name(name() + ".fetchCycles")
194 .desc("Number of cycles fetch has run and was not squashing or"
196 .prereq(fetchCycles);
199 .name(name() + ".fetchIdleCycles")
200 .desc("Number of cycles fetch was idle")
201 .prereq(fetchIdleCycles);
204 .name(name() + ".fetchSquashCycles")
205 .desc("Number of cycles fetch has spent squashing")
206 .prereq(fetchSquashCycles);
209 .name(name() + ".fetchBlockedCycles")
210 .desc("Number of cycles fetch has spent blocked")
211 .prereq(fetchBlockedCycles);
214 .name(name() + ".fetchedCacheLines")
215 .desc("Number of cache lines fetched")
216 .prereq(fetchedCacheLines);
219 .name(name() + ".fetchIcacheSquashes")
220 .desc("Number of outstanding Icache misses that were squashed")
221 .prereq(fetchIcacheSquashes);
224 .init(/* base value */ 0,
225 /* last value */ width,
227 .name(name() + ".rateDist")
228 .desc("Number of instructions fetched each cycle (Total)")
232 .name(name() + ".idleRate")
233 .desc("Percent of cycles fetch was idle")
235 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
238 .name(name() + ".branchRate")
239 .desc("Number of branch fetches per cycle")
240 .flags(Stats::total);
241 branchRate = fetchedBranches / cpu->numCycles;
244 .name(name() + ".rate")
245 .desc("Number of inst fetches per cycle")
246 .flags(Stats::total);
247 fetchRate = fetchedInsts / cpu->numCycles;
250 .name(name() + ".IFQ:count")
251 .desc("cumulative IFQ occupancy")
255 .name(name() + ".IFQ:fullCount")
256 .desc("cumulative IFQ full count")
261 .name(name() + ".IFQ:occupancy")
262 .desc("avg IFQ occupancy (inst's)")
264 IFQOccupancy = IFQCount / cpu->numCycles;
267 .name(name() + ".IFQ:latency")
268 .desc("avg IFQ occupant latency (cycle's)")
273 .name(name() + ".IFQ:fullRate")
274 .desc("fraction of time (cycles) IFQ was full")
275 .flags(Stats::total);
277 IFQFullRate = IFQFcount * Stats::constant(100) / cpu->numCycles;
280 .name(name() + ".DIS:count")
281 .desc("cumulative count of dispatched insts")
285 dispatchedSerializing
286 .name(name() + ".DIS:serializingInsts")
287 .desc("count of serializing insts dispatched")
291 dispatchedTempSerializing
292 .name(name() + ".DIS:tempSerializingInsts")
293 .desc("count of temporary serializing insts dispatched")
297 dispatchSerializeStallCycles
298 .name(name() + ".DIS:serializeStallCycles")
299 .desc("count of cycles dispatch stalled for serializing inst")
304 .name(name() + ".DIS:rate")
305 .desc("dispatched insts per cycle")
308 dispatchRate = dispatchCountStat / cpu->numCycles;
311 .name(name() + ".REG:int:full")
312 .desc("number of cycles where there were no INT registers")
316 .name(name() + ".REG:fp:full")
317 .desc("number of cycles where there were no FP registers")
319 IFQLatency = IFQOccupancy / dispatchRate;
321 branchPred.regStats();
324 template <class Impl>
326 FrontEnd<Impl>::tick()
331 // @todo: Maybe I want to just have direct communication...
332 if (fromCommit->doneSeqNum) {
333 branchPred.update(fromCommit->doneSeqNum, 0);
336 IFQCount += instBufferSize;
337 IFQFcount += instBufferSize == maxInstBufferSize;
340 if (status == IcacheAccessComplete) {
341 cacheBlkValid = true;
345 status = SerializeBlocked;
347 status = RenameBlocked;
349 } else if (status == IcacheWaitResponse || status == IcacheWaitRetry) {
350 DPRINTF(FE, "Still in Icache wait.\n");
355 if (status == RenameBlocked || status == SerializeBlocked ||
356 status == TrapPending || status == BEBlocked) {
357 // Will cause a one cycle bubble between changing state and
359 DPRINTF(FE, "In blocked status.\n");
361 fetchBlockedCycles++;
363 if (status == SerializeBlocked) {
364 dispatchSerializeStallCycles++;
368 } else if (status == QuiescePending) {
369 DPRINTF(FE, "Waiting for quiesce to execute or get squashed.\n");
371 } else if (status != IcacheAccessComplete) {
372 if (fetchCacheLineNextCycle) {
373 Fault fault = fetchCacheLine();
374 if (fault != NoFault) {
379 fetchCacheLineNextCycle = false;
381 // If miss, stall until it returns.
382 if (status == IcacheWaitResponse || status == IcacheWaitRetry) {
383 // Tell CPU to not tick me for now.
392 // Otherwise loop and process instructions.
393 // One way to hack infinite width is to set width and maxInstBufferSize
394 // both really high. Inelegant, but probably will work.
395 while (num_inst < width &&
396 instBufferSize < maxInstBufferSize) {
397 // Get instruction from cache line.
398 DynInstPtr inst = getInstFromCacheline();
401 // PC is no longer in the cache line, end fetch.
402 // Might want to check this at the end of the cycle so that
403 // there's no cycle lost to checking for a new cache line.
404 DPRINTF(FE, "Need to get new cache line\n");
405 fetchCacheLineNextCycle = true;
411 if (status == SerializeBlocked) {
415 // Possibly push into a time buffer that estimates the front end
417 instBuffer.push_back(inst);
422 if (inst->isQuiesce()) {
423 warn("%lli: Quiesce instruction encountered, halting fetch!", curTick);
424 status = QuiescePending;
429 if (inst->predTaken()) {
430 // Start over with tick?
432 } else if (freeRegs <= 0) {
433 DPRINTF(FE, "Ran out of free registers to rename to!\n");
434 status = RenameBlocked;
436 } else if (serializeNext) {
441 fetchNisnDist.sample(num_inst);
444 DPRINTF(FE, "Num insts processed: %i, Inst Buffer size: %i, Free "
445 "Regs %i\n", num_inst, instBufferSize, freeRegs);
448 template <class Impl>
450 FrontEnd<Impl>::fetchCacheLine()
452 // Read a cache line, based on the current PC.
454 // Flag to say whether or not address is physical addr.
455 unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
458 #endif // FULL_SYSTEM
459 Fault fault = NoFault;
461 if (interruptPending && flags == 0) {
465 // Align the fetch PC so it's at the start of a cache block.
466 Addr fetch_PC = icacheBlockAlignPC(PC);
468 DPRINTF(FE, "Fetching cache line starting at %#x.\n", fetch_PC);
470 // Setup the memReq to do a read of the first isntruction's address.
471 // Set the appropriate read size and flags as well.
472 memReq = new Request(0, fetch_PC, cacheBlkSize, flags,
473 fetch_PC, cpu->readCpuId(), 0);
475 // Translate the instruction request.
476 fault = cpu->translateInstReq(memReq, thread);
478 // Now do the timing access to see whether or not the instruction
479 // exists within the cache.
480 if (fault == NoFault) {
482 if (cpu->system->memctrl->badaddr(memReq->paddr) ||
483 memReq->flags & UNCACHEABLE) {
484 DPRINTF(FE, "Fetch: Bad address %#x (hopefully on a "
485 "misspeculating path!",
487 return TheISA::genMachineCheckFault();
491 // Build packet here.
492 PacketPtr data_pkt = new Packet(memReq,
493 Packet::ReadReq, Packet::Broadcast);
494 data_pkt->dataStatic(cacheData);
496 if (!icachePort.sendTiming(data_pkt)) {
497 assert(retryPkt == NULL);
498 DPRINTF(Fetch, "Out of MSHRs!\n");
499 status = IcacheWaitRetry;
505 status = IcacheWaitResponse;
508 // Note that this will set the cache block PC a bit earlier than it should
510 cacheBlkPC = fetch_PC;
514 DPRINTF(FE, "Done fetching cache line.\n");
519 template <class Impl>
521 FrontEnd<Impl>::processInst(DynInstPtr &inst)
523 if (processBarriers(inst)) {
527 Addr inst_PC = inst->readPC();
529 if (!inst->isControl()) {
530 inst->setPredTarg(inst->readNextPC());
533 if (branchPred.predict(inst, inst_PC, inst->threadNumber)) {
538 Addr next_PC = inst->readPredTarg();
540 DPRINTF(FE, "[sn:%lli] Predicted and processed inst PC %#x, next PC "
541 "%#x\n", inst->seqNum, inst_PC, next_PC);
543 // inst->setNextPC(next_PC);
545 // Not sure where I should set this
551 template <class Impl>
553 FrontEnd<Impl>::processBarriers(DynInstPtr &inst)
556 inst->setSerializeBefore();
557 serializeNext = false;
558 } else if (!inst->isSerializing() &&
559 !inst->isIprAccess() &&
560 !inst->isStoreConditional()) {
564 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
565 !inst->isSerializeHandled()) {
566 DPRINTF(FE, "Serialize before instruction encountered.\n");
568 if (!inst->isTempSerializeBefore()) {
569 dispatchedSerializing++;
570 inst->setSerializeHandled();
572 dispatchedTempSerializing++;
575 // Change status over to SerializeBlocked so that other stages know
576 // what this is blocked on.
577 status = SerializeBlocked;
581 } else if ((inst->isStoreConditional() || inst->isSerializeAfter())
582 && !inst->isSerializeHandled()) {
583 DPRINTF(FE, "Serialize after instruction encountered.\n");
585 inst->setSerializeHandled();
587 dispatchedSerializing++;
589 serializeNext = true;
595 template <class Impl>
597 FrontEnd<Impl>::handleFault(Fault &fault)
599 DPRINTF(FE, "Fault at fetch, telling commit\n");
601 // We're blocked on the back end until it handles this fault.
602 status = TrapPending;
604 // Get a sequence number.
605 InstSeqNum inst_seq = getAndIncrementInstSeq();
606 // We will use a nop in order to carry the fault.
607 ExtMachInst ext_inst = TheISA::NoopMachInst;
609 // Create a new DynInst from the dummy nop.
610 DynInstPtr instruction = new DynInst(ext_inst, PC,
613 instruction->setPredTarg(instruction->readNextPC());
614 // instruction->setThread(tid);
616 // instruction->setASID(tid);
618 instruction->setThreadState(thread);
620 instruction->traceData = NULL;
622 instruction->fault = fault;
623 instruction->setCanIssue();
624 instBuffer.push_back(instruction);
628 template <class Impl>
630 FrontEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC,
631 const bool is_branch, const bool branch_taken)
633 DPRINTF(FE, "Squashing from [sn:%lli], setting PC to %#x\n",
634 squash_num, next_PC);
636 if (fetchFault != NoFault)
637 fetchFault = NoFault;
639 while (!instBuffer.empty() &&
640 instBuffer.back()->seqNum > squash_num) {
641 DynInstPtr inst = instBuffer.back();
643 DPRINTF(FE, "Squashing instruction [sn:%lli] PC %#x\n",
644 inst->seqNum, inst->readPC());
646 inst->clearDependents();
648 instBuffer.pop_back();
651 freeRegs+= inst->numDestRegs();
654 // Copy over rename table from the back end.
655 renameTable.copyFrom(backEnd->renameTable);
659 // Update BP with proper information.
661 branchPred.squash(squash_num, next_PC, branch_taken, 0);
663 branchPred.squash(squash_num, 0);
666 // Clear the icache miss if it's outstanding.
667 if (status == IcacheWaitResponse) {
668 DPRINTF(FE, "Squashing outstanding Icache access.\n");
672 if (status == SerializeBlocked) {
673 assert(barrierInst->seqNum > squash_num);
677 // Unless this squash originated from the front end, we're probably
678 // in running mode now.
679 // Actually might want to make this latency dependent.
681 fetchCacheLineNextCycle = true;
684 template <class Impl>
685 typename Impl::DynInstPtr
686 FrontEnd<Impl>::getInst()
688 if (instBufferSize == 0) {
692 DynInstPtr inst = instBuffer.front();
694 instBuffer.pop_front();
703 template <class Impl>
705 FrontEnd<Impl>::processCacheCompletion(PacketPtr pkt)
707 DPRINTF(FE, "Processing cache completion\n");
709 // Do something here.
710 if (status != IcacheWaitResponse ||
711 pkt->req != memReq ||
713 DPRINTF(FE, "Previous fetch was squashed.\n");
714 fetchIcacheSquashes++;
720 status = IcacheAccessComplete;
722 /* if (checkStall(tid)) {
723 fetchStatus[tid] = Blocked;
725 fetchStatus[tid] = IcacheMissComplete;
728 // memcpy(cacheData, memReq->data, memReq->size);
730 // Reset the completion event to NULL.
731 // memReq->completionEvent = NULL;
737 template <class Impl>
739 FrontEnd<Impl>::addFreeRegs(int num_freed)
741 if (status == RenameBlocked && freeRegs + num_freed > 0) {
745 DPRINTF(FE, "Adding %i freed registers\n", num_freed);
747 freeRegs+= num_freed;
749 // assert(freeRegs <= numPhysRegs);
750 if (freeRegs > numPhysRegs)
751 freeRegs = numPhysRegs;
754 template <class Impl>
756 FrontEnd<Impl>::recvRetry()
758 assert(cacheBlocked);
759 if (retryPkt != NULL) {
760 assert(status == IcacheWaitRetry);
762 if (icachePort.sendTiming(retryPkt)) {
763 status = IcacheWaitResponse;
765 cacheBlocked = false;
768 // Access has been squashed since it was sent out. Just clear
769 // the cache being blocked.
770 cacheBlocked = false;
775 template <class Impl>
777 FrontEnd<Impl>::updateStatus()
779 bool serialize_block = !backEnd->robEmpty() || instBufferSize;
780 bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
781 bool ret_val = false;
783 if (status == SerializeBlocked && !serialize_block) {
784 status = SerializeComplete;
788 if (status == BEBlocked && !be_block) {
790 status = SerializeBlocked;
799 template <class Impl>
801 FrontEnd<Impl>::checkBE()
803 bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
805 if (status == Running || status == Idle) {
811 template <class Impl>
812 typename Impl::DynInstPtr
813 FrontEnd<Impl>::getInstFromCacheline()
815 if (status == SerializeComplete) {
816 DynInstPtr inst = barrierInst;
819 inst->clearSerializeBefore();
825 // @todo: Fix this magic number used here to handle word offset (and
826 // getting rid of PAL bit)
827 unsigned offset = (PC & cacheBlkMask) & ~3;
829 // PC of inst is not in this cache block
830 if (PC >= (cacheBlkPC + cacheBlkSize) || PC < cacheBlkPC || !cacheBlkValid) {
834 //////////////////////////
835 // Fetch one instruction
836 //////////////////////////
838 // Get a sequence number.
839 inst_seq = getAndIncrementInstSeq();
841 // Make sure this is a valid index.
842 assert(offset <= cacheBlkSize - sizeof(MachInst));
844 // Get the instruction from the array of the cache line.
845 inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
847 ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC);
849 // Create a new DynInst from the instruction fetched.
850 DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
853 instruction->setThreadState(thread);
855 DPRINTF(FE, "Instruction [sn:%lli] created, with PC %#x\n%s\n",
856 inst_seq, instruction->readPC(),
857 instruction->staticInst->disassemble(PC));
859 instruction->traceData =
860 Trace::getInstRecord(curTick, tc, cpu,
861 instruction->staticInst,
862 instruction->readPC(), 0);
864 // Increment stat of fetched instructions.
870 template <class Impl>
872 FrontEnd<Impl>::renameInst(DynInstPtr &inst)
874 DynInstPtr src_inst = NULL;
875 int num_src_regs = inst->numSrcRegs();
876 if (num_src_regs == 0) {
879 for (int i = 0; i < num_src_regs; ++i) {
880 src_inst = renameTable[inst->srcRegIdx(i)];
882 inst->setSrcInst(src_inst, i);
884 DPRINTF(FE, "[sn:%lli]: Src reg %i is inst [sn:%lli]\n",
885 inst->seqNum, (int)inst->srcRegIdx(i), src_inst->seqNum);
887 if (src_inst->isResultReady()) {
888 DPRINTF(FE, "Reg ready.\n");
889 inst->markSrcRegReady(i);
891 DPRINTF(FE, "Adding to dependent list.\n");
892 src_inst->addDependent(inst);
897 for (int i = 0; i < inst->numDestRegs(); ++i) {
898 RegIndex idx = inst->destRegIdx(i);
900 DPRINTF(FE, "Dest reg %i is now inst [sn:%lli], was previously "
902 (int)inst->destRegIdx(i), inst->seqNum,
903 renameTable[idx]->seqNum);
905 inst->setPrevDestInst(renameTable[idx], i);
907 renameTable[idx] = inst;
912 template <class Impl>
914 FrontEnd<Impl>::wakeFromQuiesce()
916 DPRINTF(FE, "Waking up from quiesce\n");
917 // Hopefully this is safe
921 template <class Impl>
923 FrontEnd<Impl>::switchOut()
926 cpu->signalSwitched();
929 template <class Impl>
931 FrontEnd<Impl>::doSwitchOut()
940 template <class Impl>
942 FrontEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
944 assert(freeRegs == numPhysRegs);
945 fetchCacheLineNextCycle = true;
947 cacheBlkValid = false;
950 // pTable = params->pTable;
952 fetchFault = NoFault;
953 serializeNext = false;
957 interruptPending = false;
960 template <class Impl>
962 FrontEnd<Impl>::dumpInsts()
964 cprintf("instBuffer size: %i\n", instBuffer.size());
966 InstBuffIt buff_it = instBuffer.begin();
968 for (int num = 0; buff_it != instBuffer.end(); num++) {
969 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
971 num, (*buff_it)->readPC(), (*buff_it)->threadNumber,
972 (*buff_it)->seqNum, (*buff_it)->isIssued(),
973 (*buff_it)->isSquashed());