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31 #include "config/use_checker.hh"
33 #include "sim/faults.hh"
34 #include "arch/isa_traits.hh"
35 #include "arch/utility.hh"
36 #include "base/statistics.hh"
37 #include "cpu/thread_context.hh"
38 #include "cpu/exetrace.hh"
39 #include "cpu/ozone/front_end.hh"
40 #include "mem/mem_object.hh"
41 #include "mem/packet.hh"
42 #include "mem/request.hh"
45 #include "cpu/checker/cpu.hh"
48 using namespace TheISA;
52 FrontEnd<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
54 panic("FrontEnd doesn't expect recvAtomic callback!");
60 FrontEnd<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
62 warn("FrontEnd doesn't update state from functional calls");
67 FrontEnd<Impl>::IcachePort::recvStatusChange(Status status)
69 if (status == RangeChange)
72 panic("FrontEnd doesn't expect recvStatusChange callback!");
77 FrontEnd<Impl>::IcachePort::recvTiming(PacketPtr pkt)
79 fe->processCacheCompletion(pkt);
85 FrontEnd<Impl>::IcachePort::recvRetry()
91 FrontEnd<Impl>::FrontEnd(Params *params)
94 numInstsReady(params->frontEndLatency, 0),
96 maxInstBufferSize(params->maxInstBufferSize),
97 latency(params->frontEndLatency),
98 width(params->frontEndWidth),
99 freeRegs(params->numPhysicalRegs),
100 numPhysRegs(params->numPhysicalRegs),
101 serializeNext(false),
102 interruptPending(false)
109 // Size of cache block.
112 assert(isPowerOf2(cacheBlkSize));
114 // Create mask to get rid of offset bits.
115 cacheBlkMask = (cacheBlkSize - 1);
117 // Create space to store a cache line.
118 cacheData = new uint8_t[cacheBlkSize];
120 fetchCacheLineNextCycle = true;
122 cacheBlkValid = cacheBlocked = false;
126 fetchFault = NoFault;
129 template <class Impl>
131 FrontEnd<Impl>::name() const
133 return cpu->name() + ".frontend";
136 template <class Impl>
138 FrontEnd<Impl>::setCPU(CPUType *cpu_ptr)
142 icachePort.setName(this->name() + "-iport");
146 cpu->checker->setIcachePort(&icachePort);
151 template <class Impl>
153 FrontEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
156 // @todo: Hardcoded for now. Allow this to be set by a latency.
157 fromCommit = comm->getWire(-1);
160 template <class Impl>
162 FrontEnd<Impl>::setTC(ThreadContext *tc_ptr)
167 template <class Impl>
169 FrontEnd<Impl>::regStats()
172 .name(name() + ".icacheStallCycles")
173 .desc("Number of cycles fetch is stalled on an Icache miss")
174 .prereq(icacheStallCycles);
177 .name(name() + ".fetchedInsts")
178 .desc("Number of instructions fetch has processed")
179 .prereq(fetchedInsts);
182 .name(name() + ".fetchedBranches")
183 .desc("Number of fetched branches")
184 .prereq(fetchedBranches);
187 .name(name() + ".predictedBranches")
188 .desc("Number of branches that fetch has predicted taken")
189 .prereq(predictedBranches);
192 .name(name() + ".fetchCycles")
193 .desc("Number of cycles fetch has run and was not squashing or"
195 .prereq(fetchCycles);
198 .name(name() + ".fetchIdleCycles")
199 .desc("Number of cycles fetch was idle")
200 .prereq(fetchIdleCycles);
203 .name(name() + ".fetchSquashCycles")
204 .desc("Number of cycles fetch has spent squashing")
205 .prereq(fetchSquashCycles);
208 .name(name() + ".fetchBlockedCycles")
209 .desc("Number of cycles fetch has spent blocked")
210 .prereq(fetchBlockedCycles);
213 .name(name() + ".fetchedCacheLines")
214 .desc("Number of cache lines fetched")
215 .prereq(fetchedCacheLines);
218 .name(name() + ".fetchIcacheSquashes")
219 .desc("Number of outstanding Icache misses that were squashed")
220 .prereq(fetchIcacheSquashes);
223 .init(/* base value */ 0,
224 /* last value */ width,
226 .name(name() + ".rateDist")
227 .desc("Number of instructions fetched each cycle (Total)")
231 .name(name() + ".idleRate")
232 .desc("Percent of cycles fetch was idle")
234 idleRate = fetchIdleCycles * 100 / cpu->numCycles;
237 .name(name() + ".branchRate")
238 .desc("Number of branch fetches per cycle")
239 .flags(Stats::total);
240 branchRate = fetchedBranches / cpu->numCycles;
243 .name(name() + ".rate")
244 .desc("Number of inst fetches per cycle")
245 .flags(Stats::total);
246 fetchRate = fetchedInsts / cpu->numCycles;
249 .name(name() + ".IFQ:count")
250 .desc("cumulative IFQ occupancy")
254 .name(name() + ".IFQ:fullCount")
255 .desc("cumulative IFQ full count")
260 .name(name() + ".IFQ:occupancy")
261 .desc("avg IFQ occupancy (inst's)")
263 IFQOccupancy = IFQCount / cpu->numCycles;
266 .name(name() + ".IFQ:latency")
267 .desc("avg IFQ occupant latency (cycle's)")
272 .name(name() + ".IFQ:fullRate")
273 .desc("fraction of time (cycles) IFQ was full")
274 .flags(Stats::total);
276 IFQFullRate = IFQFcount * Stats::constant(100) / cpu->numCycles;
279 .name(name() + ".DIS:count")
280 .desc("cumulative count of dispatched insts")
284 dispatchedSerializing
285 .name(name() + ".DIS:serializingInsts")
286 .desc("count of serializing insts dispatched")
290 dispatchedTempSerializing
291 .name(name() + ".DIS:tempSerializingInsts")
292 .desc("count of temporary serializing insts dispatched")
296 dispatchSerializeStallCycles
297 .name(name() + ".DIS:serializeStallCycles")
298 .desc("count of cycles dispatch stalled for serializing inst")
303 .name(name() + ".DIS:rate")
304 .desc("dispatched insts per cycle")
307 dispatchRate = dispatchCountStat / cpu->numCycles;
310 .name(name() + ".REG:int:full")
311 .desc("number of cycles where there were no INT registers")
315 .name(name() + ".REG:fp:full")
316 .desc("number of cycles where there were no FP registers")
318 IFQLatency = IFQOccupancy / dispatchRate;
320 branchPred.regStats();
323 template <class Impl>
325 FrontEnd<Impl>::tick()
330 for (int insts_to_queue = numInstsReady[-latency];
331 !instBuffer.empty() && insts_to_queue;
334 DPRINTF(FE, "Transferring instruction [sn:%lli] to the feBuffer\n",
335 instBuffer.front()->seqNum);
336 feBuffer.push_back(instBuffer.front());
337 instBuffer.pop_front();
340 numInstsReady.advance();
342 // @todo: Maybe I want to just have direct communication...
343 if (fromCommit->doneSeqNum) {
344 branchPred.update(fromCommit->doneSeqNum, 0);
347 IFQCount += instBufferSize;
348 IFQFcount += instBufferSize == maxInstBufferSize;
351 if (status == IcacheAccessComplete) {
352 cacheBlkValid = true;
356 // status = SerializeBlocked;
358 status = RenameBlocked;
360 } else if (status == IcacheWaitResponse || status == IcacheWaitRetry) {
361 DPRINTF(FE, "Still in Icache wait.\n");
366 if (status == RenameBlocked || status == SerializeBlocked ||
367 status == TrapPending || status == BEBlocked) {
368 // Will cause a one cycle bubble between changing state and
370 DPRINTF(FE, "In blocked status.\n");
372 fetchBlockedCycles++;
374 if (status == SerializeBlocked) {
375 dispatchSerializeStallCycles++;
379 } else if (status == QuiescePending) {
380 DPRINTF(FE, "Waiting for quiesce to execute or get squashed.\n");
382 } else if (status != IcacheAccessComplete) {
383 if (fetchCacheLineNextCycle) {
384 Fault fault = fetchCacheLine();
385 if (fault != NoFault) {
390 fetchCacheLineNextCycle = false;
392 // If miss, stall until it returns.
393 if (status == IcacheWaitResponse || status == IcacheWaitRetry) {
394 // Tell CPU to not tick me for now.
403 // Otherwise loop and process instructions.
404 // One way to hack infinite width is to set width and maxInstBufferSize
405 // both really high. Inelegant, but probably will work.
406 while (num_inst < width &&
407 instBufferSize < maxInstBufferSize) {
408 // Get instruction from cache line.
409 DynInstPtr inst = getInstFromCacheline();
412 // PC is no longer in the cache line, end fetch.
413 // Might want to check this at the end of the cycle so that
414 // there's no cycle lost to checking for a new cache line.
415 DPRINTF(FE, "Need to get new cache line\n");
416 fetchCacheLineNextCycle = true;
422 if (status == SerializeBlocked) {
426 // Possibly push into a time buffer that estimates the front end
428 instBuffer.push_back(inst);
434 if (inst->isQuiesce()) {
435 // warn("%lli: Quiesce instruction encountered, halting fetch!", curTick);
436 status = QuiescePending;
441 if (inst->predTaken()) {
442 // Start over with tick?
444 } else if (freeRegs <= 0) {
445 DPRINTF(FE, "Ran out of free registers to rename to!\n");
446 status = RenameBlocked;
448 } else if (serializeNext) {
453 fetchNisnDist.sample(num_inst);
456 DPRINTF(FE, "Num insts processed: %i, Inst Buffer size: %i, Free "
457 "Regs %i\n", num_inst, instBufferSize, freeRegs);
460 template <class Impl>
462 FrontEnd<Impl>::fetchCacheLine()
464 // Read a cache line, based on the current PC.
466 // Flag to say whether or not address is physical addr.
467 unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
470 #endif // FULL_SYSTEM
471 Fault fault = NoFault;
473 if (interruptPending && flags == 0) {
477 // Align the fetch PC so it's at the start of a cache block.
478 Addr fetch_PC = icacheBlockAlignPC(PC);
480 DPRINTF(FE, "Fetching cache line starting at %#x.\n", fetch_PC);
482 // Setup the memReq to do a read of the first isntruction's address.
483 // Set the appropriate read size and flags as well.
484 memReq = new Request(0, fetch_PC, cacheBlkSize, flags,
485 fetch_PC, cpu->readCpuId(), 0);
487 // Translate the instruction request.
488 fault = cpu->translateInstReq(memReq, thread);
490 // Now do the timing access to see whether or not the instruction
491 // exists within the cache.
492 if (fault == NoFault) {
494 if (cpu->system->memctrl->badaddr(memReq->paddr) ||
495 memReq->isUncacheable()) {
496 DPRINTF(FE, "Fetch: Bad address %#x (hopefully on a "
497 "misspeculating path!",
499 return TheISA::genMachineCheckFault();
503 // Build packet here.
504 PacketPtr data_pkt = new Packet(memReq,
505 Packet::ReadReq, Packet::Broadcast);
506 data_pkt->dataStatic(cacheData);
508 if (!icachePort.sendTiming(data_pkt)) {
509 assert(retryPkt == NULL);
510 DPRINTF(Fetch, "Out of MSHRs!\n");
511 status = IcacheWaitRetry;
517 status = IcacheWaitResponse;
520 // Note that this will set the cache block PC a bit earlier than it should
522 cacheBlkPC = fetch_PC;
526 DPRINTF(FE, "Done fetching cache line.\n");
531 template <class Impl>
533 FrontEnd<Impl>::processInst(DynInstPtr &inst)
535 if (processBarriers(inst)) {
539 Addr inst_PC = inst->readPC();
541 if (!inst->isControl()) {
542 inst->setPredTarg(inst->readNextPC());
545 if (branchPred.predict(inst, inst_PC, inst->threadNumber)) {
550 Addr next_PC = inst->readPredTarg();
552 DPRINTF(FE, "[sn:%lli] Predicted and processed inst PC %#x, next PC "
553 "%#x\n", inst->seqNum, inst_PC, next_PC);
555 // inst->setNextPC(next_PC);
557 // Not sure where I should set this
563 template <class Impl>
565 FrontEnd<Impl>::processBarriers(DynInstPtr &inst)
568 inst->setSerializeBefore();
569 serializeNext = false;
570 } else if (!inst->isSerializing() &&
571 !inst->isIprAccess() &&
572 !inst->isStoreConditional()) {
576 if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
577 !inst->isSerializeHandled()) {
578 DPRINTF(FE, "Serialize before instruction encountered.\n");
580 if (!inst->isTempSerializeBefore()) {
581 dispatchedSerializing++;
582 inst->setSerializeHandled();
584 dispatchedTempSerializing++;
587 // Change status over to SerializeBlocked so that other stages know
588 // what this is blocked on.
589 // status = SerializeBlocked;
591 // barrierInst = inst;
593 } else if ((inst->isStoreConditional() || inst->isSerializeAfter())
594 && !inst->isSerializeHandled()) {
595 DPRINTF(FE, "Serialize after instruction encountered.\n");
597 inst->setSerializeHandled();
599 dispatchedSerializing++;
601 serializeNext = true;
607 template <class Impl>
609 FrontEnd<Impl>::handleFault(Fault &fault)
611 DPRINTF(FE, "Fault at fetch, telling commit\n");
613 // We're blocked on the back end until it handles this fault.
614 status = TrapPending;
616 // Get a sequence number.
617 InstSeqNum inst_seq = getAndIncrementInstSeq();
618 // We will use a nop in order to carry the fault.
619 ExtMachInst ext_inst = TheISA::NoopMachInst;
621 // Create a new DynInst from the dummy nop.
622 DynInstPtr instruction = new DynInst(ext_inst, PC,
625 instruction->setPredTarg(instruction->readNextPC());
626 // instruction->setThread(tid);
628 // instruction->setASID(tid);
630 instruction->setThreadState(thread);
632 instruction->traceData = NULL;
634 instruction->fault = fault;
635 instruction->setCanIssue();
636 instBuffer.push_back(instruction);
641 template <class Impl>
643 FrontEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC,
644 const bool is_branch, const bool branch_taken)
646 DPRINTF(FE, "Squashing from [sn:%lli], setting PC to %#x\n",
647 squash_num, next_PC);
649 if (fetchFault != NoFault)
650 fetchFault = NoFault;
652 while (!instBuffer.empty() &&
653 instBuffer.back()->seqNum > squash_num) {
654 DynInstPtr inst = instBuffer.back();
656 DPRINTF(FE, "Squashing instruction [sn:%lli] PC %#x\n",
657 inst->seqNum, inst->readPC());
659 inst->clearDependents();
661 instBuffer.pop_back();
664 freeRegs+= inst->numDestRegs();
667 while (!feBuffer.empty() &&
668 feBuffer.back()->seqNum > squash_num) {
669 DynInstPtr inst = feBuffer.back();
671 DPRINTF(FE, "Squashing instruction [sn:%lli] PC %#x\n",
672 inst->seqNum, inst->readPC());
674 inst->clearDependents();
679 freeRegs+= inst->numDestRegs();
682 // Copy over rename table from the back end.
683 renameTable.copyFrom(backEnd->renameTable);
687 // Update BP with proper information.
689 branchPred.squash(squash_num, next_PC, branch_taken, 0);
691 branchPred.squash(squash_num, 0);
694 // Clear the icache miss if it's outstanding.
695 if (status == IcacheWaitResponse) {
696 DPRINTF(FE, "Squashing outstanding Icache access.\n");
700 if (status == SerializeBlocked) {
701 assert(barrierInst->seqNum > squash_num);
705 // Unless this squash originated from the front end, we're probably
706 // in running mode now.
707 // Actually might want to make this latency dependent.
709 fetchCacheLineNextCycle = true;
712 template <class Impl>
713 typename Impl::DynInstPtr
714 FrontEnd<Impl>::getInst()
716 if (feBuffer.empty()) {
720 DynInstPtr inst = feBuffer.front();
722 if (inst->isSerializeBefore() || inst->isIprAccess()) {
723 DPRINTF(FE, "Back end is getting a serialize before inst\n");
724 if (!backEnd->robEmpty()) {
725 DPRINTF(FE, "Rob is not empty yet, not returning inst\n");
728 inst->clearSerializeBefore();
731 feBuffer.pop_front();
740 template <class Impl>
742 FrontEnd<Impl>::processCacheCompletion(PacketPtr pkt)
744 DPRINTF(FE, "Processing cache completion\n");
746 // Do something here.
747 if (status != IcacheWaitResponse ||
748 pkt->req != memReq ||
750 DPRINTF(FE, "Previous fetch was squashed.\n");
751 fetchIcacheSquashes++;
757 status = IcacheAccessComplete;
759 /* if (checkStall(tid)) {
760 fetchStatus[tid] = Blocked;
762 fetchStatus[tid] = IcacheMissComplete;
765 // memcpy(cacheData, memReq->data, memReq->size);
767 // Reset the completion event to NULL.
768 // memReq->completionEvent = NULL;
774 template <class Impl>
776 FrontEnd<Impl>::addFreeRegs(int num_freed)
778 if (status == RenameBlocked && freeRegs + num_freed > 0) {
782 DPRINTF(FE, "Adding %i freed registers\n", num_freed);
784 freeRegs+= num_freed;
786 // assert(freeRegs <= numPhysRegs);
787 if (freeRegs > numPhysRegs)
788 freeRegs = numPhysRegs;
791 template <class Impl>
793 FrontEnd<Impl>::recvRetry()
795 assert(cacheBlocked);
796 if (retryPkt != NULL) {
797 assert(status == IcacheWaitRetry);
799 if (icachePort.sendTiming(retryPkt)) {
800 status = IcacheWaitResponse;
802 cacheBlocked = false;
805 // Access has been squashed since it was sent out. Just clear
806 // the cache being blocked.
807 cacheBlocked = false;
812 template <class Impl>
814 FrontEnd<Impl>::updateStatus()
816 bool serialize_block = !backEnd->robEmpty() || instBufferSize;
817 bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
818 bool ret_val = false;
820 if (status == SerializeBlocked && !serialize_block) {
821 status = SerializeComplete;
825 if (status == BEBlocked && !be_block) {
826 // if (barrierInst) {
827 // status = SerializeBlocked;
836 template <class Impl>
838 FrontEnd<Impl>::checkBE()
840 bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
842 if (status == Running || status == Idle) {
848 template <class Impl>
849 typename Impl::DynInstPtr
850 FrontEnd<Impl>::getInstFromCacheline()
853 if (status == SerializeComplete) {
854 DynInstPtr inst = barrierInst;
857 inst->clearSerializeBefore();
863 // @todo: Fix this magic number used here to handle word offset (and
864 // getting rid of PAL bit)
865 unsigned offset = (PC & cacheBlkMask) & ~3;
867 // PC of inst is not in this cache block
868 if (PC >= (cacheBlkPC + cacheBlkSize) || PC < cacheBlkPC || !cacheBlkValid) {
872 //////////////////////////
873 // Fetch one instruction
874 //////////////////////////
876 // Get a sequence number.
877 inst_seq = getAndIncrementInstSeq();
879 // Make sure this is a valid index.
880 assert(offset <= cacheBlkSize - sizeof(MachInst));
882 // Get the instruction from the array of the cache line.
883 inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
885 ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc);
887 // Create a new DynInst from the instruction fetched.
888 DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
891 instruction->setThreadState(thread);
893 DPRINTF(FE, "Instruction [sn:%lli] created, with PC %#x\n%s\n",
894 inst_seq, instruction->readPC(),
895 instruction->staticInst->disassemble(PC));
897 instruction->traceData =
898 Trace::getInstRecord(curTick, tc,
899 instruction->staticInst,
900 instruction->readPC());
902 // Increment stat of fetched instructions.
908 template <class Impl>
910 FrontEnd<Impl>::renameInst(DynInstPtr &inst)
912 DynInstPtr src_inst = NULL;
913 int num_src_regs = inst->numSrcRegs();
914 if (num_src_regs == 0) {
917 for (int i = 0; i < num_src_regs; ++i) {
918 src_inst = renameTable[inst->srcRegIdx(i)];
920 inst->setSrcInst(src_inst, i);
922 DPRINTF(FE, "[sn:%lli]: Src reg %i is inst [sn:%lli]\n",
923 inst->seqNum, (int)inst->srcRegIdx(i), src_inst->seqNum);
925 if (src_inst->isResultReady()) {
926 DPRINTF(FE, "Reg ready.\n");
927 inst->markSrcRegReady(i);
929 DPRINTF(FE, "Adding to dependent list.\n");
930 src_inst->addDependent(inst);
935 for (int i = 0; i < inst->numDestRegs(); ++i) {
936 RegIndex idx = inst->destRegIdx(i);
938 DPRINTF(FE, "Dest reg %i is now inst [sn:%lli], was previously "
940 (int)inst->destRegIdx(i), inst->seqNum,
941 renameTable[idx]->seqNum);
943 inst->setPrevDestInst(renameTable[idx], i);
945 renameTable[idx] = inst;
950 template <class Impl>
952 FrontEnd<Impl>::wakeFromQuiesce()
954 DPRINTF(FE, "Waking up from quiesce\n");
955 // Hopefully this is safe
959 template <class Impl>
961 FrontEnd<Impl>::switchOut()
964 cpu->signalSwitched();
967 template <class Impl>
969 FrontEnd<Impl>::doSwitchOut()
979 template <class Impl>
981 FrontEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
983 assert(freeRegs == numPhysRegs);
984 fetchCacheLineNextCycle = true;
986 cacheBlkValid = false;
989 // pTable = params->pTable;
991 fetchFault = NoFault;
992 serializeNext = false;
996 interruptPending = false;
999 template <class Impl>
1001 FrontEnd<Impl>::dumpInsts()
1003 cprintf("instBuffer size: %i\n", instBuffer.size());
1005 InstBuffIt buff_it = instBuffer.begin();
1007 for (int num = 0; buff_it != instBuffer.end(); num++) {
1008 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1010 num, (*buff_it)->readPC(), (*buff_it)->threadNumber,
1011 (*buff_it)->seqNum, (*buff_it)->isIssued(),
1012 (*buff_it)->isSquashed());