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31 #ifndef __CPU_OZONE_INORDER_BACK_END_HH__
32 #define __CPU_OZONE_INORDER_BACK_END_HH__
36 #include "sim/faults.hh"
37 #include "base/timebuf.hh"
38 #include "cpu/thread_context.hh"
39 #include "cpu/inst_seq.hh"
40 #include "cpu/ozone/rename_table.hh"
41 #include "cpu/ozone/thread_state.hh"
42 #include "mem/request.hh"
43 #include "sim/eventq.hh"
49 typedef typename Impl::Params Params;
50 typedef typename Impl::DynInstPtr DynInstPtr;
51 typedef typename Impl::FullCPU FullCPU;
52 typedef typename Impl::FrontEnd FrontEnd;
54 typedef typename FullCPU::OzoneTC OzoneTC;
55 typedef typename Impl::FullCPU::CommStruct CommStruct;
57 InorderBackEnd(Params *params);
59 std::string name() const;
61 void setCPU(FullCPU *cpu_ptr)
64 void setFrontEnd(FrontEnd *front_end_ptr)
65 { frontEnd = front_end_ptr; }
67 void setCommBuffer(TimeBuffer<CommStruct> *_comm)
70 void setTC(ThreadContext *tc_ptr);
72 void setThreadState(OzoneThreadState<Impl> *thread_ptr);
77 void checkInterrupts();
82 void squash(const InstSeqNum &squash_num, const Addr &next_PC);
85 void generateXCEvent() { }
87 bool robEmpty() { return instList.empty(); }
89 bool isFull() { return false; }
90 bool isBlocked() { return status == DcacheMissStoreStall ||
91 status == DcacheMissLoadStall ||
94 void fetchFault(Fault &fault);
101 void setSquashInfoFromTC();
104 InstSeqNum squashSeqNum;
107 Fault faultFromFetch;
109 bool interruptBlocked;
113 Fault read(Addr addr, T &data, unsigned flags);
116 Fault read(RequestPtr req, T &data, int load_idx);
119 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
122 Fault write(RequestPtr req, T &data, int store_idx);
124 Addr readCommitPC() { return commitPC; }
128 void switchOut() { panic("Not implemented!"); }
129 void doSwitchOut() { panic("Not implemented!"); }
130 void takeOverFrom(ThreadContext *old_tc = NULL) { panic("Not implemented!"); }
139 OzoneThreadState<Impl> *thread;
141 RenameTable<Impl> renameTable;
148 DcacheMissStoreStall,
155 class DCacheCompletionEvent : public Event
161 DCacheCompletionEvent(InorderBackEnd *_be);
163 virtual void process();
164 virtual const char *description() const;
169 friend class DCacheCompletionEvent;
171 DCacheCompletionEvent cacheCompletionEvent;
173 // MemInterface *dcacheInterface;
178 typedef typename std::list<DynInstPtr>::iterator InstListIt;
180 std::list<DynInstPtr> instList;
182 // General back end width. Used if the more specific isn't given.
189 TimeBuffer<int> numInstsToWB;
190 TimeBuffer<int>::wire instsAdded;
191 TimeBuffer<int>::wire instsToExecute;
193 TimeBuffer<CommStruct> *comm;
194 // number of cycles stalled for D-cache misses
195 Stats::Scalar dcacheStallCycles;
196 Counter lastDcacheStall;
199 template <class Impl>
202 InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
204 memReq->reset(addr, sizeof(T), flags);
206 // translate to physical address
207 Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), false);
209 // if we have a cache, do cache access too
210 if (fault == NoFault && dcacheInterface) {
212 memReq->completionEvent = NULL;
213 memReq->time = curTick;
214 MemAccessResult result = dcacheInterface->access(memReq);
216 // Ugly hack to get an event scheduled *only* if the access is
217 // a miss. We really should add first-class support for this
219 if (result != MA_HIT) {
220 // Fix this hack for keeping funcExeInst correct with loads that
221 // are executed twice.
222 memReq->completionEvent = &cacheCompletionEvent;
223 lastDcacheStall = curTick;
224 // unscheduleTickEvent();
225 status = DcacheMissLoadStall;
226 DPRINTF(IBE, "Dcache miss stall!\n");
228 // do functional access
229 DPRINTF(IBE, "Dcache hit!\n");
235 template <class Impl>
238 InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
240 memReq->reset(addr, sizeof(T), flags);
242 // translate to physical address
243 Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), true);
245 if (fault == NoFault && dcacheInterface) {
247 // memcpy(memReq->data,(uint8_t *)&data,memReq->size);
248 memReq->completionEvent = NULL;
249 memReq->time = curTick;
250 MemAccessResult result = dcacheInterface->access(memReq);
252 // Ugly hack to get an event scheduled *only* if the access is
253 // a miss. We really should add first-class support for this
255 if (result != MA_HIT) {
256 memReq->completionEvent = &cacheCompletionEvent;
257 lastDcacheStall = curTick;
258 // unscheduleTickEvent();
259 status = DcacheMissStoreStall;
260 DPRINTF(IBE, "Dcache miss stall!\n");
262 DPRINTF(IBE, "Dcache hit!\n");
266 if (res && (fault == NoFault))
267 *res = memReq->result;
271 template <class Impl>
274 InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
276 // panic("Unimplemented!");
277 // memReq->reset(addr, sizeof(T), flags);
279 // translate to physical address
280 // Fault fault = cpu->translateDataReadReq(req);
282 req->completionEvent = NULL;
285 req->data = new uint8_t[64];
286 Fault fault = cpu->read(req, data);
287 memcpy(req->data, &data, sizeof(T));
289 // if we have a cache, do cache access too
290 if (dcacheInterface) {
291 MemAccessResult result = dcacheInterface->access(req);
293 // Ugly hack to get an event scheduled *only* if the access is
294 // a miss. We really should add first-class support for this
296 if (result != MA_HIT) {
297 req->completionEvent = &cacheCompletionEvent;
298 lastDcacheStall = curTick;
299 // unscheduleTickEvent();
300 status = DcacheMissLoadStall;
301 DPRINTF(IBE, "Dcache miss load stall!\n");
303 DPRINTF(IBE, "Dcache hit!\n");
311 template <class Impl>
314 InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
316 // req->reset(addr, sizeof(T), flags);
318 // translate to physical address
319 // Fault fault = cpu->translateDataWriteReq(req);
322 req->completionEvent = NULL;
325 req->data = new uint8_t[64];
326 memcpy(req->data, (uint8_t *)&data, req->size);
330 cpu->write(req, (uint8_t &)data);
333 cpu->write(req, (uint16_t &)data);
336 cpu->write(req, (uint32_t &)data);
339 cpu->write(req, (uint64_t &)data);
342 panic("Unexpected store size!\n");
345 if (dcacheInterface) {
347 req->data = new uint8_t[64];
348 memcpy(req->data,(uint8_t *)&data,req->size);
349 req->completionEvent = NULL;
351 MemAccessResult result = dcacheInterface->access(req);
353 // Ugly hack to get an event scheduled *only* if the access is
354 // a miss. We really should add first-class support for this
356 if (result != MA_HIT) {
357 req->completionEvent = &cacheCompletionEvent;
358 lastDcacheStall = curTick;
359 // unscheduleTickEvent();
360 status = DcacheMissStoreStall;
361 DPRINTF(IBE, "Dcache miss store stall!\n");
363 DPRINTF(IBE, "Dcache hit!\n");
369 if (req->isUncacheable()) {
370 // Don't update result register (see stq_c in isa_desc)
378 if (res && (fault == NoFault))
384 #endif // __CPU_OZONE_INORDER_BACK_END_HH__