src/cpu/ozone/inorder_back_end.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_INORDER_BACK_END_HH__
  32 #define __CPU_OZONE_INORDER_BACK_END_HH__
  33
  34 #include <list>
  35
  36 #include "cpu/ozone/rename_table.hh"
  37 #include "cpu/ozone/thread_state.hh"
  38 #include "cpu/inst_seq.hh"
  39 #include "cpu/thread_context.hh"
  40 #include "cpu/timebuf.hh"
  41 #include "mem/request.hh"
  42 #include "sim/eventq.hh"
  43 #include "sim/faults.hh"
  44
  45 template <class Impl>
  46 class InorderBackEnd
  47 {
  48   public:
  49     typedef typename Impl::Params Params;
  50     typedef typename Impl::DynInstPtr DynInstPtr;
  51     typedef typename Impl::FullCPU FullCPU;
  52     typedef typename Impl::FrontEnd FrontEnd;
  53
  54     typedef typename FullCPU::OzoneTC OzoneTC;
  55     typedef typename Impl::FullCPU::CommStruct CommStruct;
  56
  57     InorderBackEnd(Params *params);
  58
  59     std::string name() const;
  60
  61     void setCPU(FullCPU *cpu_ptr)
  62     { cpu = cpu_ptr; }
  63
  64     void setFrontEnd(FrontEnd *front_end_ptr)
  65     { frontEnd = front_end_ptr; }
  66
  67     void setCommBuffer(TimeBuffer<CommStruct> *_comm)
  68     { comm = _comm; }
  69
  70     void setTC(ThreadContext *tc_ptr);
  71
  72     void setThreadState(OzoneThreadState<Impl> *thread_ptr);
  73
  74     void regStats() { }
  75
  76 #if FULL_SYSTEM
  77     void checkInterrupts();
  78 #endif
  79
  80     void tick();
  81     void executeInsts();
  82     void squash(const InstSeqNum &squash_num, const Addr &next_PC);
  83
  84     void squashFromXC();
  85     void generateXCEvent() { }
  86
  87     bool robEmpty() { return instList.empty(); }
  88
  89     bool isFull() { return false; }
  90     bool isBlocked() { return status == DcacheMissStoreStall ||
  91                            status == DcacheMissLoadStall ||
  92                            interruptBlocked; }
  93
  94     void fetchFault(Fault &fault);
  95
  96     void dumpInsts();
  97
  98   private:
  99     void handleFault();
 100
 101     void setSquashInfoFromTC();
 102
 103     bool squashPending;
 104     InstSeqNum squashSeqNum;
 105     Addr squashNextPC;
 106
 107     Fault faultFromFetch;
 108
 109     bool interruptBlocked;
 110
 111   public:
 112     template <class T>
 113     Fault read(Addr addr, T &data, unsigned flags);
 114
 115     template <class T>
 116     Fault read(RequestPtr req, T &data, int load_idx);
 117
 118     template <class T>
 119     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 120
 121     template <class T>
 122     Fault write(RequestPtr req, T &data, int store_idx);
 123
 124     Addr readCommitPC() { return commitPC; }
 125
 126     Addr commitPC;
 127
 128     void switchOut() { panic("Not implemented!"); }
 129     void doSwitchOut() { panic("Not implemented!"); }
 130     void takeOverFrom(ThreadContext *old_tc = NULL) { panic("Not implemented!"); }
 131
 132   public:
 133     FullCPU *cpu;
 134
 135     FrontEnd *frontEnd;
 136
 137     ThreadContext *tc;
 138
 139     OzoneThreadState<Impl> *thread;
 140
 141     RenameTable<Impl> renameTable;
 142
 143   protected:
 144     enum Status {
 145         Running,
 146         Idle,
 147         DcacheMissLoadStall,
 148         DcacheMissStoreStall,
 149         DcacheMissComplete,
 150         Blocked
 151     };
 152
 153     Status status;
 154
 155     class DCacheCompletionEvent : public Event
 156     {
 157       private:
 158         InorderBackEnd *be;
 159
 160       public:
 161         DCacheCompletionEvent(InorderBackEnd *_be);
 162
 163         virtual void process();
 164         virtual const char *description() const;
 165
 166         DynInstPtr inst;
 167     };
 168
 169     friend class DCacheCompletionEvent;
 170
 171     DCacheCompletionEvent cacheCompletionEvent;
 172
 173 //    MemInterface *dcacheInterface;
 174
 175     RequestPtr memReq;
 176
 177   private:
 178     typedef typename std::list<DynInstPtr>::iterator InstListIt;
 179
 180     std::list<DynInstPtr> instList;
 181
 182     // General back end width. Used if the more specific isn't given.
 183     int width;
 184
 185     int latency;
 186
 187     int squashLatency;
 188
 189     TimeBuffer<int> numInstsToWB;
 190     TimeBuffer<int>::wire instsAdded;
 191     TimeBuffer<int>::wire instsToExecute;
 192
 193     TimeBuffer<CommStruct> *comm;
 194     // number of cycles stalled for D-cache misses
 195     Stats::Scalar dcacheStallCycles;
 196     Counter lastDcacheStall;
 197 };
 198
 199 template <class Impl>
 200 template <class T>
 201 Fault
 202 InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
 203 {
 204     memReq->reset(addr, sizeof(T), flags);
 205
 206     // translate to physical address
 207     Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), false);
 208
 209     // if we have a cache, do cache access too
 210     if (fault == NoFault && dcacheInterface) {
 211         memReq->cmd = Read;
 212         memReq->completionEvent = NULL;
 213         memReq->time = curTick();
 214         MemAccessResult result = dcacheInterface->access(memReq);
 215
 216         // Ugly hack to get an event scheduled *only* if the access is
 217         // a miss.  We really should add first-class support for this
 218         // at some point.
 219         if (result != MA_HIT) {
 220             // Fix this hack for keeping funcExeInst correct with loads that
 221             // are executed twice.
 222             memReq->completionEvent = &cacheCompletionEvent;
 223             lastDcacheStall = curTick();
 224 //          unscheduleTickEvent();
 225             status = DcacheMissLoadStall;
 226             DPRINTF(IBE, "Dcache miss stall!\n");
 227         } else {
 228             // do functional access
 229             DPRINTF(IBE, "Dcache hit!\n");
 230         }
 231     }
 232     return fault;
 233 }
 234
 235 template <class Impl>
 236 template <class T>
 237 Fault
 238 InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
 239 {
 240     memReq->reset(addr, sizeof(T), flags);
 241
 242     // translate to physical address
 243     Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), true);
 244
 245     if (fault == NoFault && dcacheInterface) {
 246         memReq->cmd = Write;
 247 //      memcpy(memReq->data,(uint8_t *)&data,memReq->size);
 248         memReq->completionEvent = NULL;
 249         memReq->time = curTick();
 250         MemAccessResult result = dcacheInterface->access(memReq);
 251
 252         // Ugly hack to get an event scheduled *only* if the access is
 253         // a miss.  We really should add first-class support for this
 254         // at some point.
 255         if (result != MA_HIT) {
 256             memReq->completionEvent = &cacheCompletionEvent;
 257             lastDcacheStall = curTick();
 258 //          unscheduleTickEvent();
 259             status = DcacheMissStoreStall;
 260             DPRINTF(IBE, "Dcache miss stall!\n");
 261         } else {
 262             DPRINTF(IBE, "Dcache hit!\n");
 263         }
 264     }
 265
 266     if (res && (fault == NoFault))
 267         *res = memReq->result;
 268     return fault;
 269 }
 270
 271 template <class Impl>
 272 template <class T>
 273 Fault
 274 InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
 275 {
 276 //    panic("Unimplemented!");
 277 //    memReq->reset(addr, sizeof(T), flags);
 278
 279     // translate to physical address
 280 //    Fault fault = cpu->translateDataReadReq(req);
 281     req->cmd = Read;
 282     req->completionEvent = NULL;
 283     req->time = curTick();
 284     assert(!req->data);
 285     req->data = new uint8_t[64];
 286     Fault fault = cpu->read(req, data);
 287     memcpy(req->data, &data, sizeof(T));
 288
 289     // if we have a cache, do cache access too
 290     if (dcacheInterface) {
 291         MemAccessResult result = dcacheInterface->access(req);
 292
 293         // Ugly hack to get an event scheduled *only* if the access is
 294         // a miss.  We really should add first-class support for this
 295         // at some point.
 296         if (result != MA_HIT) {
 297             req->completionEvent = &cacheCompletionEvent;
 298             lastDcacheStall = curTick();
 299 //          unscheduleTickEvent();
 300             status = DcacheMissLoadStall;
 301             DPRINTF(IBE, "Dcache miss load stall!\n");
 302         } else {
 303             DPRINTF(IBE, "Dcache hit!\n");
 304
 305         }
 306     }
 307
 308     return NoFault;
 309 }
 310
 311 template <class Impl>
 312 template <class T>
 313 Fault
 314 InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
 315 {
 316 //    req->reset(addr, sizeof(T), flags);
 317
 318     // translate to physical address
 319 //    Fault fault = cpu->translateDataWriteReq(req);
 320
 321     req->cmd = Write;
 322     req->completionEvent = NULL;
 323     req->time = curTick();
 324     assert(!req->data);
 325     req->data = new uint8_t[64];
 326     memcpy(req->data, (uint8_t *)&data, req->size);
 327
 328     switch(req->size) {
 329       case 1:
 330         cpu->write(req, (uint8_t &)data);
 331         break;
 332       case 2:
 333         cpu->write(req, (uint16_t &)data);
 334         break;
 335       case 4:
 336         cpu->write(req, (uint32_t &)data);
 337         break;
 338       case 8:
 339         cpu->write(req, (uint64_t &)data);
 340         break;
 341       default:
 342         panic("Unexpected store size!\n");
 343     }
 344
 345     if (dcacheInterface) {
 346         req->cmd = Write;
 347         req->data = new uint8_t[64];
 348         memcpy(req->data,(uint8_t *)&data,req->size);
 349         req->completionEvent = NULL;
 350         req->time = curTick();
 351         MemAccessResult result = dcacheInterface->access(req);
 352
 353         // Ugly hack to get an event scheduled *only* if the access is
 354         // a miss.  We really should add first-class support for this
 355         // at some point.
 356         if (result != MA_HIT) {
 357             req->completionEvent = &cacheCompletionEvent;
 358             lastDcacheStall = curTick();
 359 //          unscheduleTickEvent();
 360             status = DcacheMissStoreStall;
 361             DPRINTF(IBE, "Dcache miss store stall!\n");
 362         } else {
 363             DPRINTF(IBE, "Dcache hit!\n");
 364
 365         }
 366     }
 367 /*
 368     if (req->isLLSC()) {
 369         if (req->isUncacheable()) {
 370             // Don't update result register (see stq_c in isa_desc)
 371             req->result = 2;
 372         } else {
 373             req->result = 1;
 374         }
 375     }
 376 */
 377 /*
 378     if (res && (fault == NoFault))
 379         *res = req->result;
 380         */
 381     return NoFault;
 382 }
 383
 384 #endif // __CPU_OZONE_INORDER_BACK_END_HH__