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31 #ifndef __CPU_OZONE_INORDER_BACK_END_HH__
32 #define __CPU_OZONE_INORDER_BACK_END_HH__
36 #include "cpu/ozone/rename_table.hh"
37 #include "cpu/ozone/thread_state.hh"
38 #include "cpu/inst_seq.hh"
39 #include "cpu/thread_context.hh"
40 #include "cpu/timebuf.hh"
41 #include "mem/request.hh"
42 #include "sim/eventq.hh"
43 #include "sim/faults.hh"
49 typedef typename Impl::Params Params;
50 typedef typename Impl::DynInstPtr DynInstPtr;
51 typedef typename Impl::FullCPU FullCPU;
52 typedef typename Impl::FrontEnd FrontEnd;
54 typedef typename FullCPU::OzoneTC OzoneTC;
55 typedef typename Impl::FullCPU::CommStruct CommStruct;
57 InorderBackEnd(Params *params);
59 std::string name() const;
61 void setCPU(FullCPU *cpu_ptr)
64 void setFrontEnd(FrontEnd *front_end_ptr)
65 { frontEnd = front_end_ptr; }
67 void setCommBuffer(TimeBuffer<CommStruct> *_comm)
70 void setTC(ThreadContext *tc_ptr);
72 void setThreadState(OzoneThreadState<Impl> *thread_ptr);
76 void checkInterrupts();
80 void squash(const InstSeqNum &squash_num, const Addr &next_PC);
83 void generateXCEvent() { }
85 bool robEmpty() { return instList.empty(); }
87 bool isFull() { return false; }
88 bool isBlocked() { return status == DcacheMissStoreStall ||
89 status == DcacheMissLoadStall ||
92 void fetchFault(Fault &fault);
99 void setSquashInfoFromTC();
102 InstSeqNum squashSeqNum;
105 Fault faultFromFetch;
107 bool interruptBlocked;
111 Fault read(Addr addr, T &data, unsigned flags);
114 Fault read(RequestPtr req, T &data, int load_idx);
117 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
120 Fault write(RequestPtr req, T &data, int store_idx);
122 Addr readCommitPC() { return commitPC; }
126 void switchOut() { panic("Not implemented!"); }
127 void doSwitchOut() { panic("Not implemented!"); }
128 void takeOverFrom(ThreadContext *old_tc = NULL) { panic("Not implemented!"); }
137 OzoneThreadState<Impl> *thread;
139 RenameTable<Impl> renameTable;
146 DcacheMissStoreStall,
153 class DCacheCompletionEvent : public Event
159 DCacheCompletionEvent(InorderBackEnd *_be);
161 virtual void process();
162 virtual const char *description() const;
167 friend class DCacheCompletionEvent;
169 DCacheCompletionEvent cacheCompletionEvent;
171 // MemInterface *dcacheInterface;
176 typedef typename std::list<DynInstPtr>::iterator InstListIt;
178 std::list<DynInstPtr> instList;
180 // General back end width. Used if the more specific isn't given.
187 TimeBuffer<int> numInstsToWB;
188 TimeBuffer<int>::wire instsAdded;
189 TimeBuffer<int>::wire instsToExecute;
191 TimeBuffer<CommStruct> *comm;
192 // number of cycles stalled for D-cache misses
193 Stats::Scalar dcacheStallCycles;
194 Counter lastDcacheStall;
197 template <class Impl>
200 InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
202 memReq->reset(addr, sizeof(T), flags);
204 // translate to physical address
205 Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), false);
207 // if we have a cache, do cache access too
208 if (fault == NoFault && dcacheInterface) {
210 memReq->completionEvent = NULL;
211 memReq->time = curTick();
212 MemAccessResult result = dcacheInterface->access(memReq);
214 // Ugly hack to get an event scheduled *only* if the access is
215 // a miss. We really should add first-class support for this
217 if (result != MA_HIT) {
218 // Fix this hack for keeping funcExeInst correct with loads that
219 // are executed twice.
220 memReq->completionEvent = &cacheCompletionEvent;
221 lastDcacheStall = curTick();
222 // unscheduleTickEvent();
223 status = DcacheMissLoadStall;
224 DPRINTF(IBE, "Dcache miss stall!\n");
226 // do functional access
227 DPRINTF(IBE, "Dcache hit!\n");
233 template <class Impl>
236 InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
238 memReq->reset(addr, sizeof(T), flags);
240 // translate to physical address
241 Fault fault = cpu->dtb->translateAtomic(memReq, thread->getTC(), true);
243 if (fault == NoFault && dcacheInterface) {
245 // memcpy(memReq->data,(uint8_t *)&data,memReq->size);
246 memReq->completionEvent = NULL;
247 memReq->time = curTick();
248 MemAccessResult result = dcacheInterface->access(memReq);
250 // Ugly hack to get an event scheduled *only* if the access is
251 // a miss. We really should add first-class support for this
253 if (result != MA_HIT) {
254 memReq->completionEvent = &cacheCompletionEvent;
255 lastDcacheStall = curTick();
256 // unscheduleTickEvent();
257 status = DcacheMissStoreStall;
258 DPRINTF(IBE, "Dcache miss stall!\n");
260 DPRINTF(IBE, "Dcache hit!\n");
264 if (res && (fault == NoFault))
265 *res = memReq->result;
269 template <class Impl>
272 InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
274 // panic("Unimplemented!");
275 // memReq->reset(addr, sizeof(T), flags);
277 // translate to physical address
278 // Fault fault = cpu->translateDataReadReq(req);
280 req->completionEvent = NULL;
281 req->time = curTick();
283 req->data = new uint8_t[64];
284 Fault fault = cpu->read(req, data);
285 memcpy(req->data, &data, sizeof(T));
287 // if we have a cache, do cache access too
288 if (dcacheInterface) {
289 MemAccessResult result = dcacheInterface->access(req);
291 // Ugly hack to get an event scheduled *only* if the access is
292 // a miss. We really should add first-class support for this
294 if (result != MA_HIT) {
295 req->completionEvent = &cacheCompletionEvent;
296 lastDcacheStall = curTick();
297 // unscheduleTickEvent();
298 status = DcacheMissLoadStall;
299 DPRINTF(IBE, "Dcache miss load stall!\n");
301 DPRINTF(IBE, "Dcache hit!\n");
309 template <class Impl>
312 InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
314 // req->reset(addr, sizeof(T), flags);
316 // translate to physical address
317 // Fault fault = cpu->translateDataWriteReq(req);
320 req->completionEvent = NULL;
321 req->time = curTick();
323 req->data = new uint8_t[64];
324 memcpy(req->data, (uint8_t *)&data, req->size);
328 cpu->write(req, (uint8_t &)data);
331 cpu->write(req, (uint16_t &)data);
334 cpu->write(req, (uint32_t &)data);
337 cpu->write(req, (uint64_t &)data);
340 panic("Unexpected store size!\n");
343 if (dcacheInterface) {
345 req->data = new uint8_t[64];
346 memcpy(req->data,(uint8_t *)&data,req->size);
347 req->completionEvent = NULL;
348 req->time = curTick();
349 MemAccessResult result = dcacheInterface->access(req);
351 // Ugly hack to get an event scheduled *only* if the access is
352 // a miss. We really should add first-class support for this
354 if (result != MA_HIT) {
355 req->completionEvent = &cacheCompletionEvent;
356 lastDcacheStall = curTick();
357 // unscheduleTickEvent();
358 status = DcacheMissStoreStall;
359 DPRINTF(IBE, "Dcache miss store stall!\n");
361 DPRINTF(IBE, "Dcache hit!\n");
367 if (req->isUncacheable()) {
368 // Don't update result register (see stq_c in isa_desc)
376 if (res && (fault == NoFault))
382 #endif // __CPU_OZONE_INORDER_BACK_END_HH__