src/cpu/ozone/inorder_back_end.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_INORDER_BACK_END_HH__
  32 #define __CPU_OZONE_INORDER_BACK_END_HH__
  33
  34 #include <list>
  35
  36 #include "sim/faults.hh"
  37 #include "base/timebuf.hh"
  38 #include "cpu/thread_context.hh"
  39 #include "cpu/inst_seq.hh"
  40 #include "cpu/ozone/rename_table.hh"
  41 #include "cpu/ozone/thread_state.hh"
  42 #include "mem/request.hh"
  43 #include "sim/eventq.hh"
  44
  45 template <class Impl>
  46 class InorderBackEnd
  47 {
  48   public:
  49     typedef typename Impl::Params Params;
  50     typedef typename Impl::DynInstPtr DynInstPtr;
  51     typedef typename Impl::FullCPU FullCPU;
  52     typedef typename Impl::FrontEnd FrontEnd;
  53
  54     typedef typename FullCPU::OzoneTC OzoneTC;
  55     typedef typename Impl::FullCPU::CommStruct CommStruct;
  56
  57     InorderBackEnd(Params *params);
  58
  59     std::string name() const;
  60
  61     void setCPU(FullCPU *cpu_ptr)
  62     { cpu = cpu_ptr; }
  63
  64     void setFrontEnd(FrontEnd *front_end_ptr)
  65     { frontEnd = front_end_ptr; }
  66
  67     void setCommBuffer(TimeBuffer<CommStruct> *_comm)
  68     { comm = _comm; }
  69
  70     void setTC(ThreadContext *tc_ptr);
  71
  72     void setThreadState(OzoneThreadState<Impl> *thread_ptr);
  73
  74     void regStats() { }
  75
  76 #if FULL_SYSTEM
  77     void checkInterrupts();
  78 #endif
  79
  80     void tick();
  81     void executeInsts();
  82     void squash(const InstSeqNum &squash_num, const Addr &next_PC);
  83
  84     void squashFromXC();
  85     void generateXCEvent() { }
  86
  87     bool robEmpty() { return instList.empty(); }
  88
  89     bool isFull() { return false; }
  90     bool isBlocked() { return status == DcacheMissStoreStall ||
  91                            status == DcacheMissLoadStall ||
  92                            interruptBlocked; }
  93
  94     void fetchFault(Fault &fault);
  95
  96     void dumpInsts();
  97
  98   private:
  99     void handleFault();
 100
 101     void setSquashInfoFromTC();
 102
 103     bool squashPending;
 104     InstSeqNum squashSeqNum;
 105     Addr squashNextPC;
 106
 107     Fault faultFromFetch;
 108
 109     bool interruptBlocked;
 110
 111   public:
 112     template <class T>
 113     Fault read(Addr addr, T &data, unsigned flags);
 114
 115     template <class T>
 116     Fault read(RequestPtr req, T &data, int load_idx);
 117
 118     template <class T>
 119     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 120
 121     template <class T>
 122     Fault write(RequestPtr req, T &data, int store_idx);
 123
 124     Addr readCommitPC() { return commitPC; }
 125
 126     Addr commitPC;
 127
 128     void switchOut() { panic("Not implemented!"); }
 129     void doSwitchOut() { panic("Not implemented!"); }
 130     void takeOverFrom(ThreadContext *old_tc = NULL) { panic("Not implemented!"); }
 131
 132   public:
 133     FullCPU *cpu;
 134
 135     FrontEnd *frontEnd;
 136
 137     ThreadContext *tc;
 138
 139     OzoneThreadState<Impl> *thread;
 140
 141     RenameTable<Impl> renameTable;
 142
 143   protected:
 144     enum Status {
 145         Running,
 146         Idle,
 147         DcacheMissLoadStall,
 148         DcacheMissStoreStall,
 149         DcacheMissComplete,
 150         Blocked
 151     };
 152
 153     Status status;
 154
 155     class DCacheCompletionEvent : public Event
 156     {
 157       private:
 158         InorderBackEnd *be;
 159
 160       public:
 161         DCacheCompletionEvent(InorderBackEnd *_be);
 162
 163         virtual void process();
 164         virtual const char *description() const;
 165
 166         DynInstPtr inst;
 167     };
 168
 169     friend class DCacheCompletionEvent;
 170
 171     DCacheCompletionEvent cacheCompletionEvent;
 172
 173 //    MemInterface *dcacheInterface;
 174
 175     RequestPtr memReq;
 176
 177   private:
 178     typedef typename std::list<DynInstPtr>::iterator InstListIt;
 179
 180     std::list<DynInstPtr> instList;
 181
 182     // General back end width. Used if the more specific isn't given.
 183     int width;
 184
 185     int latency;
 186
 187     int squashLatency;
 188
 189     TimeBuffer<int> numInstsToWB;
 190     TimeBuffer<int>::wire instsAdded;
 191     TimeBuffer<int>::wire instsToExecute;
 192
 193     TimeBuffer<CommStruct> *comm;
 194     // number of cycles stalled for D-cache misses
 195     Stats::Scalar<> dcacheStallCycles;
 196     Counter lastDcacheStall;
 197 };
 198
 199 template <class Impl>
 200 template <class T>
 201 Fault
 202 InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
 203 {
 204     memReq->reset(addr, sizeof(T), flags);
 205
 206     // translate to physical address
 207     Fault fault = cpu->translateDataReadReq(memReq);
 208
 209     // if we have a cache, do cache access too
 210     if (fault == NoFault && dcacheInterface) {
 211         memReq->cmd = Read;
 212         memReq->completionEvent = NULL;
 213         memReq->time = curTick;
 214         memReq->flags &= ~INST_READ;
 215         MemAccessResult result = dcacheInterface->access(memReq);
 216
 217         // Ugly hack to get an event scheduled *only* if the access is
 218         // a miss.  We really should add first-class support for this
 219         // at some point.
 220         if (result != MA_HIT) {
 221             // Fix this hack for keeping funcExeInst correct with loads that
 222             // are executed twice.
 223             memReq->completionEvent = &cacheCompletionEvent;
 224             lastDcacheStall = curTick;
 225 //          unscheduleTickEvent();
 226             status = DcacheMissLoadStall;
 227             DPRINTF(IBE, "Dcache miss stall!\n");
 228         } else {
 229             // do functional access
 230             DPRINTF(IBE, "Dcache hit!\n");
 231         }
 232     }
 233 /*
 234     if (!dcacheInterface && (memReq->isUncacheable()))
 235         recordEvent("Uncached Read");
 236 */
 237     return fault;
 238 }
 239
 240 template <class Impl>
 241 template <class T>
 242 Fault
 243 InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
 244 {
 245     memReq->reset(addr, sizeof(T), flags);
 246
 247     // translate to physical address
 248     Fault fault = cpu->translateDataWriteReq(memReq);
 249
 250     if (fault == NoFault && dcacheInterface) {
 251         memReq->cmd = Write;
 252 //      memcpy(memReq->data,(uint8_t *)&data,memReq->size);
 253         memReq->completionEvent = NULL;
 254         memReq->time = curTick;
 255         memReq->flags &= ~INST_READ;
 256         MemAccessResult result = dcacheInterface->access(memReq);
 257
 258         // Ugly hack to get an event scheduled *only* if the access is
 259         // a miss.  We really should add first-class support for this
 260         // at some point.
 261         if (result != MA_HIT) {
 262             memReq->completionEvent = &cacheCompletionEvent;
 263             lastDcacheStall = curTick;
 264 //          unscheduleTickEvent();
 265             status = DcacheMissStoreStall;
 266             DPRINTF(IBE, "Dcache miss stall!\n");
 267         } else {
 268             DPRINTF(IBE, "Dcache hit!\n");
 269         }
 270     }
 271
 272     if (res && (fault == NoFault))
 273         *res = memReq->result;
 274 /*
 275     if (!dcacheInterface && (memReq->isUncacheable()))
 276         recordEvent("Uncached Write");
 277 */
 278     return fault;
 279 }
 280
 281 template <class Impl>
 282 template <class T>
 283 Fault
 284 InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
 285 {
 286 //    panic("Unimplemented!");
 287 //    memReq->reset(addr, sizeof(T), flags);
 288
 289     // translate to physical address
 290 //    Fault fault = cpu->translateDataReadReq(req);
 291     req->cmd = Read;
 292     req->completionEvent = NULL;
 293     req->time = curTick;
 294     assert(!req->data);
 295     req->data = new uint8_t[64];
 296     req->flags &= ~INST_READ;
 297     Fault fault = cpu->read(req, data);
 298     memcpy(req->data, &data, sizeof(T));
 299
 300     // if we have a cache, do cache access too
 301     if (dcacheInterface) {
 302         MemAccessResult result = dcacheInterface->access(req);
 303
 304         // Ugly hack to get an event scheduled *only* if the access is
 305         // a miss.  We really should add first-class support for this
 306         // at some point.
 307         if (result != MA_HIT) {
 308             req->completionEvent = &cacheCompletionEvent;
 309             lastDcacheStall = curTick;
 310 //          unscheduleTickEvent();
 311             status = DcacheMissLoadStall;
 312             DPRINTF(IBE, "Dcache miss load stall!\n");
 313         } else {
 314             DPRINTF(IBE, "Dcache hit!\n");
 315
 316         }
 317     }
 318
 319 /*
 320     if (!dcacheInterface && (req->isUncacheable()))
 321         recordEvent("Uncached Read");
 322 */
 323     return NoFault;
 324 }
 325
 326 template <class Impl>
 327 template <class T>
 328 Fault
 329 InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
 330 {
 331 //    req->reset(addr, sizeof(T), flags);
 332
 333     // translate to physical address
 334 //    Fault fault = cpu->translateDataWriteReq(req);
 335
 336     req->cmd = Write;
 337     req->completionEvent = NULL;
 338     req->time = curTick;
 339     assert(!req->data);
 340     req->data = new uint8_t[64];
 341     memcpy(req->data, (uint8_t *)&data, req->size);
 342
 343     switch(req->size) {
 344       case 1:
 345         cpu->write(req, (uint8_t &)data);
 346         break;
 347       case 2:
 348         cpu->write(req, (uint16_t &)data);
 349         break;
 350       case 4:
 351         cpu->write(req, (uint32_t &)data);
 352         break;
 353       case 8:
 354         cpu->write(req, (uint64_t &)data);
 355         break;
 356       default:
 357         panic("Unexpected store size!\n");
 358     }
 359
 360     if (dcacheInterface) {
 361         req->cmd = Write;
 362         req->data = new uint8_t[64];
 363         memcpy(req->data,(uint8_t *)&data,req->size);
 364         req->completionEvent = NULL;
 365         req->time = curTick;
 366         req->flags &= ~INST_READ;
 367         MemAccessResult result = dcacheInterface->access(req);
 368
 369         // Ugly hack to get an event scheduled *only* if the access is
 370         // a miss.  We really should add first-class support for this
 371         // at some point.
 372         if (result != MA_HIT) {
 373             req->completionEvent = &cacheCompletionEvent;
 374             lastDcacheStall = curTick;
 375 //          unscheduleTickEvent();
 376             status = DcacheMissStoreStall;
 377             DPRINTF(IBE, "Dcache miss store stall!\n");
 378         } else {
 379             DPRINTF(IBE, "Dcache hit!\n");
 380
 381         }
 382     }
 383 /*
 384     if (req->isLocked()) {
 385         if (req->isUncacheable()) {
 386             // Don't update result register (see stq_c in isa_desc)
 387             req->result = 2;
 388         } else {
 389             req->result = 1;
 390         }
 391     }
 392 */
 393 /*
 394     if (res && (fault == NoFault))
 395         *res = req->result;
 396         */
 397 /*
 398     if (!dcacheInterface && (req->isUncacheable()))
 399         recordEvent("Uncached Write");
 400 */
 401     return NoFault;
 402 }
 403
 404 #endif // __CPU_OZONE_INORDER_BACK_END_HH__