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31 #ifndef __CPU_OZONE_INORDER_BACK_END_HH__
32 #define __CPU_OZONE_INORDER_BACK_END_HH__
36 #include "arch/faults.hh"
37 #include "base/timebuf.hh"
38 #include "cpu/thread_context.hh"
39 #include "cpu/inst_seq.hh"
40 #include "cpu/ozone/rename_table.hh"
41 #include "cpu/ozone/thread_state.hh"
42 #include "mem/request.hh"
43 #include "sim/eventq.hh"
49 typedef typename Impl::Params Params;
50 typedef typename Impl::DynInstPtr DynInstPtr;
51 typedef typename Impl::FullCPU FullCPU;
52 typedef typename Impl::FrontEnd FrontEnd;
54 typedef typename FullCPU::OzoneTC OzoneTC;
55 typedef typename Impl::FullCPU::CommStruct CommStruct;
57 InorderBackEnd(Params *params);
59 std::string name() const;
61 void setCPU(FullCPU *cpu_ptr)
64 void setFrontEnd(FrontEnd *front_end_ptr)
65 { frontEnd = front_end_ptr; }
67 void setCommBuffer(TimeBuffer<CommStruct> *_comm)
70 void setTC(ThreadContext *tc_ptr);
72 void setThreadState(OzoneThreadState<Impl> *thread_ptr);
77 void checkInterrupts();
82 void squash(const InstSeqNum &squash_num, const Addr &next_PC);
85 void generateXCEvent() { }
87 bool robEmpty() { return instList.empty(); }
89 bool isFull() { return false; }
90 bool isBlocked() { return status == DcacheMissStoreStall ||
91 status == DcacheMissLoadStall ||
94 void fetchFault(Fault &fault);
101 void setSquashInfoFromTC();
104 InstSeqNum squashSeqNum;
107 Fault faultFromFetch;
109 bool interruptBlocked;
113 Fault read(Addr addr, T &data, unsigned flags);
116 Fault read(RequestPtr req, T &data, int load_idx);
119 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
122 Fault write(RequestPtr req, T &data, int store_idx);
124 Addr readCommitPC() { return commitPC; }
128 void switchOut() { panic("Not implemented!"); }
129 void doSwitchOut() { panic("Not implemented!"); }
130 void takeOverFrom(ThreadContext *old_tc = NULL) { panic("Not implemented!"); }
139 OzoneThreadState<Impl> *thread;
141 RenameTable<Impl> renameTable;
148 DcacheMissStoreStall,
155 class DCacheCompletionEvent : public Event
161 DCacheCompletionEvent(InorderBackEnd *_be);
163 virtual void process();
164 virtual const char *description();
169 friend class DCacheCompletionEvent;
171 DCacheCompletionEvent cacheCompletionEvent;
173 // MemInterface *dcacheInterface;
178 typedef typename std::list<DynInstPtr>::iterator InstListIt;
180 std::list<DynInstPtr> instList;
182 // General back end width. Used if the more specific isn't given.
189 TimeBuffer<int> numInstsToWB;
190 TimeBuffer<int>::wire instsAdded;
191 TimeBuffer<int>::wire instsToExecute;
193 TimeBuffer<CommStruct> *comm;
194 // number of cycles stalled for D-cache misses
195 Stats::Scalar<> dcacheStallCycles;
196 Counter lastDcacheStall;
199 template <class Impl>
202 InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
204 memReq->reset(addr, sizeof(T), flags);
206 // translate to physical address
207 Fault fault = cpu->translateDataReadReq(memReq);
209 // if we have a cache, do cache access too
210 if (fault == NoFault && dcacheInterface) {
212 memReq->completionEvent = NULL;
213 memReq->time = curTick;
214 memReq->flags &= ~INST_READ;
215 MemAccessResult result = dcacheInterface->access(memReq);
217 // Ugly hack to get an event scheduled *only* if the access is
218 // a miss. We really should add first-class support for this
220 if (result != MA_HIT) {
221 // Fix this hack for keeping funcExeInst correct with loads that
222 // are executed twice.
223 memReq->completionEvent = &cacheCompletionEvent;
224 lastDcacheStall = curTick;
225 // unscheduleTickEvent();
226 status = DcacheMissLoadStall;
227 DPRINTF(IBE, "Dcache miss stall!\n");
229 // do functional access
230 DPRINTF(IBE, "Dcache hit!\n");
234 if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
235 recordEvent("Uncached Read");
240 template <class Impl>
243 InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
245 #if FULL_SYSTEM && defined(TARGET_ALPHA)
246 if (req->flags & LOCKED) {
247 req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
248 req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
253 error = thread->mem->read(req, data);
254 data = LittleEndianGuest::gtoh(data);
259 template <class Impl>
262 InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
264 memReq->reset(addr, sizeof(T), flags);
266 // translate to physical address
267 Fault fault = cpu->translateDataWriteReq(memReq);
269 if (fault == NoFault && dcacheInterface) {
271 // memcpy(memReq->data,(uint8_t *)&data,memReq->size);
272 memReq->completionEvent = NULL;
273 memReq->time = curTick;
274 memReq->flags &= ~INST_READ;
275 MemAccessResult result = dcacheInterface->access(memReq);
277 // Ugly hack to get an event scheduled *only* if the access is
278 // a miss. We really should add first-class support for this
280 if (result != MA_HIT) {
281 memReq->completionEvent = &cacheCompletionEvent;
282 lastDcacheStall = curTick;
283 // unscheduleTickEvent();
284 status = DcacheMissStoreStall;
285 DPRINTF(IBE, "Dcache miss stall!\n");
287 DPRINTF(IBE, "Dcache hit!\n");
291 if (res && (fault == NoFault))
292 *res = memReq->result;
294 if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
295 recordEvent("Uncached Write");
300 template <class Impl>
303 InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
305 #if FULL_SYSTEM && defined(TARGET_ALPHA)
308 // If this is a store conditional, act appropriately
309 if (req->flags & LOCKED) {
312 if (req->flags & UNCACHEABLE) {
313 // Don't update result register (see stq_c in isa_desc)
315 xc->setStCondFailures(0);//Needed? [RGD]
317 bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
318 Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
319 req->result = lock_flag;
321 ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
322 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
323 xc->setStCondFailures(xc->readStCondFailures() + 1);
324 if (((xc->readStCondFailures()) % 100000) == 0) {
325 std::cerr << "Warning: "
326 << xc->readStCondFailures()
327 << " consecutive store conditional failures "
328 << "on cpu " << req->xc->readCpuId()
333 else xc->setStCondFailures(0);
337 // Need to clear any locked flags on other proccessors for
338 // this address. Only do this for succsful Store Conditionals
339 // and all other stores (WH64?). Unsuccessful Store
340 // Conditionals would have returned above, and wouldn't fall
342 for (int i = 0; i < cpu->system->execContexts.size(); i++){
343 xc = cpu->system->execContexts[i];
344 if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
345 (req->paddr & ~0xf)) {
346 xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
351 return thread->mem->write(req, (T)LittleEndianGuest::htog(data));
355 template <class Impl>
358 InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
360 // panic("Unimplemented!");
361 // memReq->reset(addr, sizeof(T), flags);
363 // translate to physical address
364 // Fault fault = cpu->translateDataReadReq(req);
366 req->completionEvent = NULL;
369 req->data = new uint8_t[64];
370 req->flags &= ~INST_READ;
371 Fault fault = cpu->read(req, data);
372 memcpy(req->data, &data, sizeof(T));
374 // if we have a cache, do cache access too
375 if (dcacheInterface) {
376 MemAccessResult result = dcacheInterface->access(req);
378 // Ugly hack to get an event scheduled *only* if the access is
379 // a miss. We really should add first-class support for this
381 if (result != MA_HIT) {
382 req->completionEvent = &cacheCompletionEvent;
383 lastDcacheStall = curTick;
384 // unscheduleTickEvent();
385 status = DcacheMissLoadStall;
386 DPRINTF(IBE, "Dcache miss load stall!\n");
388 DPRINTF(IBE, "Dcache hit!\n");
394 if (!dcacheInterface && (req->flags & UNCACHEABLE))
395 recordEvent("Uncached Read");
400 template <class Impl>
403 InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
405 // req->reset(addr, sizeof(T), flags);
407 // translate to physical address
408 // Fault fault = cpu->translateDataWriteReq(req);
411 req->completionEvent = NULL;
414 req->data = new uint8_t[64];
415 memcpy(req->data, (uint8_t *)&data, req->size);
419 cpu->write(req, (uint8_t &)data);
422 cpu->write(req, (uint16_t &)data);
425 cpu->write(req, (uint32_t &)data);
428 cpu->write(req, (uint64_t &)data);
431 panic("Unexpected store size!\n");
434 if (dcacheInterface) {
436 req->data = new uint8_t[64];
437 memcpy(req->data,(uint8_t *)&data,req->size);
438 req->completionEvent = NULL;
440 req->flags &= ~INST_READ;
441 MemAccessResult result = dcacheInterface->access(req);
443 // Ugly hack to get an event scheduled *only* if the access is
444 // a miss. We really should add first-class support for this
446 if (result != MA_HIT) {
447 req->completionEvent = &cacheCompletionEvent;
448 lastDcacheStall = curTick;
449 // unscheduleTickEvent();
450 status = DcacheMissStoreStall;
451 DPRINTF(IBE, "Dcache miss store stall!\n");
453 DPRINTF(IBE, "Dcache hit!\n");
458 if (req->flags & LOCKED) {
459 if (req->flags & UNCACHEABLE) {
460 // Don't update result register (see stq_c in isa_desc)
468 if (res && (fault == NoFault))
472 if (!dcacheInterface && (req->flags & UNCACHEABLE))
473 recordEvent("Uncached Write");
478 #endif // __CPU_OZONE_INORDER_BACK_END_HH__