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31 #include "arch/types.hh"
32 #include "config/the_isa.hh"
33 #include "cpu/ozone/inorder_back_end.hh"
34 #include "cpu/ozone/thread_state.hh"
35 #include "sim/faults.hh"
38 InorderBackEnd<Impl>::InorderBackEnd(Params *params)
39 : squashPending(false),
42 faultFromFetch(NoFault),
43 interruptBlocked(false),
44 cacheCompletionEvent(this),
45 dcacheInterface(params->dcacheInterface),
46 width(params->backEndWidth),
47 latency(params->backEndLatency),
48 squashLatency(params->backEndSquashLatency),
49 numInstsToWB(0, latency + 1)
51 instsAdded = numInstsToWB.getWire(latency);
52 instsToExecute = numInstsToWB.getWire(0);
55 memReq->data = new uint8_t[64];
61 InorderBackEnd<Impl>::name() const
63 return cpu->name() + ".inorderbackend";
68 InorderBackEnd<Impl>::setXC(ExecContext *xc_ptr)
76 InorderBackEnd<Impl>::setThreadState(OzoneThreadState<Impl> *thread_ptr)
79 thread->setFuncExeInst(0);
84 InorderBackEnd<Impl>::checkInterrupts()
86 //Check if there are any outstanding interrupts
87 //Handle the interrupts
92 if (thread->readMiscRegNoEffect(IPR_ASTRR))
93 panic("asynchronous traps not implemented\n");
95 if (thread->readMiscRegNoEffect(IPR_SIRR)) {
96 for (int i = INTLEVEL_SOFTWARE_MIN;
97 i < INTLEVEL_SOFTWARE_MAX; i++) {
98 if (thread->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
99 // See table 4-19 of the 21164 hardware reference
100 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
101 summary |= (ULL(1) << i);
106 uint64_t interrupts = cpu->intr_status();
109 for (int i = INTLEVEL_EXTERNAL_MIN;
110 i < INTLEVEL_EXTERNAL_MAX; i++) {
111 if (interrupts & (ULL(1) << i)) {
112 // See table 4-19 of the 21164 hardware reference
114 summary |= (ULL(1) << i);
119 if (ipl && ipl > thread->readMiscRegNoEffect(IPR_IPLR)) {
120 thread->noSquashFromTC = true;
122 thread->setMiscRegNoEffect(IPR_ISR, summary);
123 thread->setMiscRegNoEffect(IPR_INTID, ipl);
124 Fault(new InterruptFault)->invoke(xc);
125 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
126 thread->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
128 // May need to go 1 inst prior
129 squashPending = true;
131 thread->noSquashFromTC = false;
133 setSquashInfoFromXC();
137 template <class Impl>
139 InorderBackEnd<Impl>::tick()
141 // Squash due to an external source
142 // Not sure if this or an interrupt has higher priority
144 squash(squashSeqNum, squashNextPC);
148 // if (interrupt) then set thread PC, stall front end, record that
149 // I'm waiting for it to drain. (for now just squash)
150 if (FullSystem && (interruptBlocked || cpu->checkInterrupts(tc))) {
152 interruptBlocked = true;
154 } else if (robEmpty() && (PC & 0x3)) {
155 // Will need to let the front end continue a bit until
156 // we're out of pal mode. Hopefully we never get into an
158 interruptBlocked = false;
160 interruptBlocked = false;
166 if (status != DcacheMissLoadStall &&
167 status != DcacheMissStoreStall) {
168 for (int i = 0; i < width && (*instsAdded) < width; ++i) {
169 DynInstPtr inst = frontEnd->getInst();
174 instList.push_back(inst);
179 if (faultFromFetch && robEmpty() && frontEnd->isEmpty()) {
187 template <class Impl>
189 InorderBackEnd<Impl>::executeInsts()
191 bool completed_last_inst = true;
192 int insts_to_execute = *instsToExecute;
195 while (insts_to_execute > 0) {
196 assert(!instList.empty());
197 DynInstPtr inst = instList.front();
199 commitPC = inst->readPC();
201 thread->setPC(commitPC);
202 thread->setNextPC(inst->readNextPC());
209 assert(!thread->noSquashFromTC && !thread->trapPending);
210 oldpc = thread->readPC();
211 cpu->system->pcEventQueue.service(
212 thread->getXCProxy());
214 } while (oldpc != thread->readPC());
216 DPRINTF(IBE, "PC skip function event, stopping commit\n");
217 completed_last_inst = false;
218 squashPending = true;
223 Fault inst_fault = NoFault;
225 if (status == DcacheMissComplete) {
226 DPRINTF(IBE, "Completing inst [sn:%lli]\n", inst->seqNum);
228 } else if (inst->isMemRef() && status != DcacheMissComplete &&
229 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
230 DPRINTF(IBE, "Initiating mem op inst [sn:%lli] PC: %#x\n",
231 inst->seqNum, inst->readPC());
233 cacheCompletionEvent.inst = inst;
234 inst_fault = inst->initiateAcc();
235 if (inst_fault == NoFault &&
236 status != DcacheMissLoadStall &&
237 status != DcacheMissStoreStall) {
238 inst_fault = inst->completeAcc();
240 ++thread->funcExeInst;
242 DPRINTF(IBE, "Executing inst [sn:%lli] PC: %#x\n",
243 inst->seqNum, inst->readPC());
244 inst_fault = inst->execute();
245 ++thread->funcExeInst;
248 // Will need to be able to break this loop in case the load
249 // misses. Split access/complete ops would be useful here
250 // with writeback events.
251 if (status == DcacheMissLoadStall) {
252 *instsToExecute = insts_to_execute;
254 completed_last_inst = false;
256 } else if (status == DcacheMissStoreStall) {
257 // Figure out how to fix this hack. Probably have DcacheMissLoad
258 // vs DcacheMissStore.
259 *instsToExecute = insts_to_execute;
260 completed_last_inst = false;
262 instList.pop_front();
264 if (inst->traceData) {
265 inst->traceData->finalize();
269 // Don't really need to stop for a store stall as long as
270 // the memory system is able to handle store forwarding
271 // and such. Breaking out might help avoid the cache
272 // interface becoming blocked.
277 inst->setResultReady();
278 inst->setCanCommit();
280 instList.pop_front();
285 if (inst->traceData) {
286 inst->traceData->finalize();
287 inst->traceData = NULL;
290 if (inst_fault != NoFault) {
291 DPRINTF(IBE, "Inst [sn:%lli] PC %#x has a fault\n",
292 inst->seqNum, inst->readPC());
294 assert(!thread->noSquashFromTC);
296 thread->noSquashFromTC = true;
298 // Consider holding onto the trap and waiting until the trap event
299 // happens for this to be executed.
300 inst_fault->invoke(xc);
302 // Exit state update mode to avoid accidental updating.
303 thread->noSquashFromTC = false;
305 squashPending = true;
307 completed_last_inst = false;
311 for (int i = 0; i < inst->numDestRegs(); ++i) {
312 renameTable[inst->destRegIdx(i)] = inst;
313 thread->renameTable[inst->destRegIdx(i)] = inst;
317 inst->clearDependents();
319 comm->access(0)->doneSeqNum = inst->seqNum;
321 if (inst->mispredicted()) {
322 squash(inst->seqNum, inst->readNextPC());
324 thread->setNextPC(inst->readNextPC());
327 } else if (squashPending) {
328 // Something external happened that caused the CPU to squash.
329 // Break out of commit and handle the squash next cycle.
332 // If it didn't mispredict, then it executed fine. Send back its
333 // registers and BP info? What about insts that may still have
334 // latency, like loads? Probably can send back the information after
337 // keep an instruction count
342 frontEnd->addFreeRegs(freed_regs);
344 assert(insts_to_execute >= 0);
346 // Should only advance this if I have executed all instructions.
347 if (insts_to_execute == 0) {
348 numInstsToWB.advance();
351 // Should I set the PC to the next PC here? What do I set next PC to?
352 if (completed_last_inst) {
353 thread->setPC(thread->readNextPC());
354 thread->setNextPC(thread->readPC() + sizeof(MachInst));
358 setSquashInfoFromXC();
362 template <class Impl>
364 InorderBackEnd<Impl>::handleFault()
366 DPRINTF(Commit, "Handling fault from fetch\n");
368 assert(!thread->noSquashFromTC);
370 thread->noSquashFromTC = true;
372 // Consider holding onto the trap and waiting until the trap event
373 // happens for this to be executed.
374 faultFromFetch->invoke(xc);
376 // Exit state update mode to avoid accidental updating.
377 thread->noSquashFromTC = false;
379 squashPending = true;
381 setSquashInfoFromXC();
384 template <class Impl>
386 InorderBackEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC)
388 DPRINTF(IBE, "Squashing from [sn:%lli], setting PC to %#x\n",
389 squash_num, next_PC);
391 InstListIt squash_it = --(instList.end());
395 while (!instList.empty() && (*squash_it)->seqNum > squash_num) {
396 DynInstPtr inst = *squash_it;
398 DPRINTF(IBE, "Squashing instruction PC %#x, [sn:%lli].\n",
402 // May cause problems with misc regs
403 freed_regs+= inst->numDestRegs();
404 inst->clearDependents();
409 frontEnd->addFreeRegs(freed_regs);
411 for (int i = 0; i < latency+1; ++i) {
412 numInstsToWB.advance();
415 squashPending = false;
417 // Probably want to make sure that this squash is the one that set the
418 // thread into noSquashFromTC mode.
419 thread->noSquashFromTC = false;
421 // Tell front end to squash, reset PC to new one.
422 frontEnd->squash(squash_num, next_PC);
424 faultFromFetch = NULL;
427 template <class Impl>
429 InorderBackEnd<Impl>::squashFromXC()
431 // Record that I need to squash
432 squashPending = true;
434 thread->noSquashFromTC = true;
437 template <class Impl>
439 InorderBackEnd<Impl>::setSquashInfoFromXC()
441 // Need to handle the case of the instList being empty. In that case
442 // probably any number works, except maybe with stores in the store buffer.
443 squashSeqNum = instList.empty() ? 0 : instList.front()->seqNum - 1;
445 squashNextPC = thread->PC;
448 template <class Impl>
450 InorderBackEnd<Impl>::fetchFault(Fault &fault)
452 faultFromFetch = fault;
455 template <class Impl>
457 InorderBackEnd<Impl>::dumpInsts()
462 InstListIt inst_list_it = instList.begin();
464 cprintf("Inst list size: %i\n", instList.size());
466 while (inst_list_it != instList.end())
468 cprintf("Instruction:%i\n",
470 if (!(*inst_list_it)->isSquashed()) {
471 if (!(*inst_list_it)->isIssued()) {
473 cprintf("Count:%i\n", valid_num);
474 } else if ((*inst_list_it)->isMemRef() &&
475 !(*inst_list_it)->memOpDone) {
476 // Loads that have not been marked as executed still count
477 // towards the total instructions.
479 cprintf("Count:%i\n", valid_num);
483 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
484 "Issued:%i\nSquashed:%i\n",
485 (*inst_list_it)->readPC(),
486 (*inst_list_it)->seqNum,
487 (*inst_list_it)->threadNumber,
488 (*inst_list_it)->isIssued(),
489 (*inst_list_it)->isSquashed());
491 if ((*inst_list_it)->isMemRef()) {
492 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
502 template <class Impl>
503 InorderBackEnd<Impl>::DCacheCompletionEvent::DCacheCompletionEvent(
505 : Event(&mainEventQueue, CPU_Tick_Pri), be(_be)
507 // this->setFlags(Event::AutoDelete);
510 template <class Impl>
512 InorderBackEnd<Impl>::DCacheCompletionEvent::process()
515 be->status = DcacheMissComplete;
518 template <class Impl>
520 InorderBackEnd<Impl>::DCacheCompletionEvent::description() const
522 return "DCache completion";