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31 #include "sim/faults.hh"
32 #include "arch/types.hh"
33 #include "config/the_isa.hh"
34 #include "cpu/ozone/inorder_back_end.hh"
35 #include "cpu/ozone/thread_state.hh"
38 InorderBackEnd<Impl>::InorderBackEnd(Params *params)
39 : squashPending(false),
42 faultFromFetch(NoFault),
43 interruptBlocked(false),
44 cacheCompletionEvent(this),
45 dcacheInterface(params->dcacheInterface),
46 width(params->backEndWidth),
47 latency(params->backEndLatency),
48 squashLatency(params->backEndSquashLatency),
49 numInstsToWB(0, latency + 1)
51 instsAdded = numInstsToWB.getWire(latency);
52 instsToExecute = numInstsToWB.getWire(0);
55 memReq->data = new uint8_t[64];
61 InorderBackEnd<Impl>::name() const
63 return cpu->name() + ".inorderbackend";
68 InorderBackEnd<Impl>::setXC(ExecContext *xc_ptr)
76 InorderBackEnd<Impl>::setThreadState(OzoneThreadState<Impl> *thread_ptr)
79 thread->setFuncExeInst(0);
85 InorderBackEnd<Impl>::checkInterrupts()
87 //Check if there are any outstanding interrupts
88 //Handle the interrupts
93 if (thread->readMiscRegNoEffect(IPR_ASTRR))
94 panic("asynchronous traps not implemented\n");
96 if (thread->readMiscRegNoEffect(IPR_SIRR)) {
97 for (int i = INTLEVEL_SOFTWARE_MIN;
98 i < INTLEVEL_SOFTWARE_MAX; i++) {
99 if (thread->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
100 // See table 4-19 of the 21164 hardware reference
101 ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
102 summary |= (ULL(1) << i);
107 uint64_t interrupts = cpu->intr_status();
110 for (int i = INTLEVEL_EXTERNAL_MIN;
111 i < INTLEVEL_EXTERNAL_MAX; i++) {
112 if (interrupts & (ULL(1) << i)) {
113 // See table 4-19 of the 21164 hardware reference
115 summary |= (ULL(1) << i);
120 if (ipl && ipl > thread->readMiscRegNoEffect(IPR_IPLR)) {
121 thread->inSyscall = true;
123 thread->setMiscRegNoEffect(IPR_ISR, summary);
124 thread->setMiscRegNoEffect(IPR_INTID, ipl);
125 Fault(new InterruptFault)->invoke(xc);
126 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
127 thread->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
129 // May need to go 1 inst prior
130 squashPending = true;
132 thread->inSyscall = false;
134 setSquashInfoFromXC();
139 template <class Impl>
141 InorderBackEnd<Impl>::tick()
143 // Squash due to an external source
144 // Not sure if this or an interrupt has higher priority
146 squash(squashSeqNum, squashNextPC);
150 // if (interrupt) then set thread PC, stall front end, record that
151 // I'm waiting for it to drain. (for now just squash)
153 if (interruptBlocked || cpu->checkInterrupts(tc)) {
155 interruptBlocked = true;
157 } else if (robEmpty() && (PC & 0x3)) {
158 // Will need to let the front end continue a bit until
159 // we're out of pal mode. Hopefully we never get into an
161 interruptBlocked = false;
163 interruptBlocked = false;
170 if (status != DcacheMissLoadStall &&
171 status != DcacheMissStoreStall) {
172 for (int i = 0; i < width && (*instsAdded) < width; ++i) {
173 DynInstPtr inst = frontEnd->getInst();
178 instList.push_back(inst);
184 if (faultFromFetch && robEmpty() && frontEnd->isEmpty()) {
195 template <class Impl>
197 InorderBackEnd<Impl>::executeInsts()
199 bool completed_last_inst = true;
200 int insts_to_execute = *instsToExecute;
203 while (insts_to_execute > 0) {
204 assert(!instList.empty());
205 DynInstPtr inst = instList.front();
207 commitPC = inst->readPC();
209 thread->setPC(commitPC);
210 thread->setNextPC(inst->readNextPC());
217 assert(!thread->inSyscall && !thread->trapPending);
218 oldpc = thread->readPC();
219 cpu->system->pcEventQueue.service(
220 thread->getXCProxy());
222 } while (oldpc != thread->readPC());
224 DPRINTF(IBE, "PC skip function event, stopping commit\n");
225 completed_last_inst = false;
226 squashPending = true;
231 Fault inst_fault = NoFault;
233 if (status == DcacheMissComplete) {
234 DPRINTF(IBE, "Completing inst [sn:%lli]\n", inst->seqNum);
236 } else if (inst->isMemRef() && status != DcacheMissComplete &&
237 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
238 DPRINTF(IBE, "Initiating mem op inst [sn:%lli] PC: %#x\n",
239 inst->seqNum, inst->readPC());
241 cacheCompletionEvent.inst = inst;
242 inst_fault = inst->initiateAcc();
243 if (inst_fault == NoFault &&
244 status != DcacheMissLoadStall &&
245 status != DcacheMissStoreStall) {
246 inst_fault = inst->completeAcc();
248 ++thread->funcExeInst;
250 DPRINTF(IBE, "Executing inst [sn:%lli] PC: %#x\n",
251 inst->seqNum, inst->readPC());
252 inst_fault = inst->execute();
253 ++thread->funcExeInst;
256 // Will need to be able to break this loop in case the load
257 // misses. Split access/complete ops would be useful here
258 // with writeback events.
259 if (status == DcacheMissLoadStall) {
260 *instsToExecute = insts_to_execute;
262 completed_last_inst = false;
264 } else if (status == DcacheMissStoreStall) {
265 // Figure out how to fix this hack. Probably have DcacheMissLoad
266 // vs DcacheMissStore.
267 *instsToExecute = insts_to_execute;
268 completed_last_inst = false;
270 instList.pop_front();
272 if (inst->traceData) {
273 inst->traceData->finalize();
277 // Don't really need to stop for a store stall as long as
278 // the memory system is able to handle store forwarding
279 // and such. Breaking out might help avoid the cache
280 // interface becoming blocked.
285 inst->setResultReady();
286 inst->setCanCommit();
288 instList.pop_front();
293 if (inst->traceData) {
294 inst->traceData->finalize();
295 inst->traceData = NULL;
298 if (inst_fault != NoFault) {
300 DPRINTF(IBE, "Inst [sn:%lli] PC %#x has a fault\n",
301 inst->seqNum, inst->readPC());
303 assert(!thread->inSyscall);
305 thread->inSyscall = true;
307 // Consider holding onto the trap and waiting until the trap event
308 // happens for this to be executed.
309 inst_fault->invoke(xc);
311 // Exit state update mode to avoid accidental updating.
312 thread->inSyscall = false;
314 squashPending = true;
316 // Generate trap squash event.
317 // generateTrapEvent(tid);
318 completed_last_inst = false;
320 #else // !FULL_SYSTEM
321 panic("fault (%d) detected @ PC %08p", inst_fault,
323 #endif // FULL_SYSTEM
326 for (int i = 0; i < inst->numDestRegs(); ++i) {
327 renameTable[inst->destRegIdx(i)] = inst;
328 thread->renameTable[inst->destRegIdx(i)] = inst;
332 inst->clearDependents();
334 comm->access(0)->doneSeqNum = inst->seqNum;
336 if (inst->mispredicted()) {
337 squash(inst->seqNum, inst->readNextPC());
339 thread->setNextPC(inst->readNextPC());
342 } else if (squashPending) {
343 // Something external happened that caused the CPU to squash.
344 // Break out of commit and handle the squash next cycle.
347 // If it didn't mispredict, then it executed fine. Send back its
348 // registers and BP info? What about insts that may still have
349 // latency, like loads? Probably can send back the information after
352 // keep an instruction count
357 frontEnd->addFreeRegs(freed_regs);
359 assert(insts_to_execute >= 0);
361 // Should only advance this if I have executed all instructions.
362 if (insts_to_execute == 0) {
363 numInstsToWB.advance();
366 // Should I set the PC to the next PC here? What do I set next PC to?
367 if (completed_last_inst) {
368 thread->setPC(thread->readNextPC());
369 thread->setNextPC(thread->readPC() + sizeof(MachInst));
373 setSquashInfoFromXC();
377 template <class Impl>
379 InorderBackEnd<Impl>::handleFault()
381 DPRINTF(Commit, "Handling fault from fetch\n");
383 assert(!thread->inSyscall);
385 thread->inSyscall = true;
387 // Consider holding onto the trap and waiting until the trap event
388 // happens for this to be executed.
389 faultFromFetch->invoke(xc);
391 // Exit state update mode to avoid accidental updating.
392 thread->inSyscall = false;
394 squashPending = true;
396 setSquashInfoFromXC();
399 template <class Impl>
401 InorderBackEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC)
403 DPRINTF(IBE, "Squashing from [sn:%lli], setting PC to %#x\n",
404 squash_num, next_PC);
406 InstListIt squash_it = --(instList.end());
410 while (!instList.empty() && (*squash_it)->seqNum > squash_num) {
411 DynInstPtr inst = *squash_it;
413 DPRINTF(IBE, "Squashing instruction PC %#x, [sn:%lli].\n",
417 // May cause problems with misc regs
418 freed_regs+= inst->numDestRegs();
419 inst->clearDependents();
424 frontEnd->addFreeRegs(freed_regs);
426 for (int i = 0; i < latency+1; ++i) {
427 numInstsToWB.advance();
430 squashPending = false;
432 // Probably want to make sure that this squash is the one that set the
433 // thread into inSyscall mode.
434 thread->inSyscall = false;
436 // Tell front end to squash, reset PC to new one.
437 frontEnd->squash(squash_num, next_PC);
439 faultFromFetch = NULL;
442 template <class Impl>
444 InorderBackEnd<Impl>::squashFromXC()
446 // Record that I need to squash
447 squashPending = true;
449 thread->inSyscall = true;
452 template <class Impl>
454 InorderBackEnd<Impl>::setSquashInfoFromXC()
456 // Need to handle the case of the instList being empty. In that case
457 // probably any number works, except maybe with stores in the store buffer.
458 squashSeqNum = instList.empty() ? 0 : instList.front()->seqNum - 1;
460 squashNextPC = thread->PC;
463 template <class Impl>
465 InorderBackEnd<Impl>::fetchFault(Fault &fault)
467 faultFromFetch = fault;
470 template <class Impl>
472 InorderBackEnd<Impl>::dumpInsts()
477 InstListIt inst_list_it = instList.begin();
479 cprintf("Inst list size: %i\n", instList.size());
481 while (inst_list_it != instList.end())
483 cprintf("Instruction:%i\n",
485 if (!(*inst_list_it)->isSquashed()) {
486 if (!(*inst_list_it)->isIssued()) {
488 cprintf("Count:%i\n", valid_num);
489 } else if ((*inst_list_it)->isMemRef() &&
490 !(*inst_list_it)->memOpDone) {
491 // Loads that have not been marked as executed still count
492 // towards the total instructions.
494 cprintf("Count:%i\n", valid_num);
498 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
499 "Issued:%i\nSquashed:%i\n",
500 (*inst_list_it)->readPC(),
501 (*inst_list_it)->seqNum,
502 (*inst_list_it)->threadNumber,
503 (*inst_list_it)->isIssued(),
504 (*inst_list_it)->isSquashed());
506 if ((*inst_list_it)->isMemRef()) {
507 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
517 template <class Impl>
518 InorderBackEnd<Impl>::DCacheCompletionEvent::DCacheCompletionEvent(
520 : Event(&mainEventQueue, CPU_Tick_Pri), be(_be)
522 // this->setFlags(Event::AutoDelete);
525 template <class Impl>
527 InorderBackEnd<Impl>::DCacheCompletionEvent::process()
530 be->status = DcacheMissComplete;
533 template <class Impl>
535 InorderBackEnd<Impl>::DCacheCompletionEvent::description() const
537 return "DCache completion";