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32 // Current ordering allows for 0 cycle added-to-scheduled. Could maybe fake
33 // it; either do in reverse order, or have added instructions put into a
34 // different ready queue that, in scheduleRreadyInsts(), gets put onto the
35 // normal ready queue. This would however give only a one cycle delay,
36 // but probably is more flexible to actually add in a delay parameter than
37 // just running it backwards.
41 #include "cpu/ozone/inst_queue.hh"
42 #include "sim/core.hh"
45 InstQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
47 InstQueue<Impl> *iq_ptr)
48 : Event(&mainEventQueue, Stat_Event_Pri),
49 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr)
51 this->setFlags(Event::AutoDelete);
56 InstQueue<Impl>::FUCompletion::process()
58 iqPtr->processFUCompletion(inst, fuIdx);
64 InstQueue<Impl>::FUCompletion::description() const
66 return "Functional unit completion";
70 InstQueue<Impl>::InstQueue(Params *params)
71 : dcacheInterface(params->dcacheInterface),
72 // fuPool(params->fuPool),
73 numEntries(params->numIQEntries),
74 totalWidth(params->issueWidth),
75 // numPhysIntRegs(params->numPhysIntRegs),
76 // numPhysFloatRegs(params->numPhysFloatRegs),
77 commitToIEWDelay(params->commitToIEWDelay)
81 // numThreads = params->numberOfThreads;
84 //Initialize thread IQ counts
85 for (ThreadID tid = 0; tid <numThreads; tid++) {
89 // Initialize the number of free IQ entries.
90 freeEntries = numEntries;
92 // Set the number of physical registers as the number of int + float
93 // numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
95 // DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs);
97 //Create an entry for each physical register within the
99 // dependGraph = new DependencyEntry[numPhysRegs];
101 // Resize the register scoreboard.
102 // regScoreboard.resize(numPhysRegs);
104 //Initialize Mem Dependence Units
105 for (ThreadID tid = 0; tid < numThreads; tid++) {
106 memDepUnit[tid].init(params, tid);
107 memDepUnit[tid].setIQ(this);
110 // Initialize all the head pointers to point to NULL, and all the
111 // entries as unready.
112 // Note that in actuality, the registers corresponding to the logical
113 // registers start off as ready. However this doesn't matter for the
114 // IQ as the instruction should have been correctly told if those
115 // registers are ready in rename. Thus it can all be initialized as
117 for (int i = 0; i < numPhysRegs; ++i) {
118 dependGraph[i].next = NULL;
119 dependGraph[i].inst = NULL;
120 regScoreboard[i] = false;
123 for (ThreadID tid = 0; tid < numThreads; ++tid) {
124 squashedSeqNum[tid] = 0;
127 for (int i = 0; i < Num_OpClasses; ++i) {
128 queueOnList[i] = false;
129 readyIt[i] = listOrder.end();
132 string policy = params->smtIQPolicy;
134 //Convert string to lowercase
135 std::transform(policy.begin(), policy.end(), policy.begin(),
136 (int(*)(int)) tolower);
138 //Figure out resource sharing policy
139 if (policy == "dynamic") {
142 //Set Max Entries to Total ROB Capacity
143 for (ThreadID tid = 0; tid < numThreads; tid++) {
144 maxEntries[tid] = numEntries;
147 } else if (policy == "partitioned") {
148 iqPolicy = Partitioned;
150 //@todo:make work if part_amt doesnt divide evenly.
151 int part_amt = numEntries / numThreads;
153 //Divide ROB up evenly
154 for (ThreadID tid = 0; tid < numThreads; tid++) {
155 maxEntries[tid] = part_amt;
158 DPRINTF(Fetch, "IQ sharing policy set to Partitioned:"
159 "%i entries per thread.\n",part_amt);
161 } else if (policy == "threshold") {
162 iqPolicy = Threshold;
164 double threshold = (double)params->smtIQThreshold / 100;
166 int thresholdIQ = (int)((double)threshold * numEntries);
168 //Divide up by threshold amount
169 for (ThreadID tid = 0; tid < numThreads; tid++) {
170 maxEntries[tid] = thresholdIQ;
173 DPRINTF(Fetch, "IQ sharing policy set to Threshold:"
174 "%i entries per thread.\n",thresholdIQ);
176 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
177 "Partitioned, Threshold}");
182 template <class Impl>
183 InstQueue<Impl>::~InstQueue()
185 // Clear the dependency graph
187 DependencyEntry *curr;
188 DependencyEntry *prev;
190 for (int i = 0; i < numPhysRegs; ++i) {
191 curr = dependGraph[i].next;
194 DependencyEntry::mem_alloc_counter--;
203 if (dependGraph[i].inst) {
204 dependGraph[i].inst = NULL;
207 dependGraph[i].next = NULL;
210 assert(DependencyEntry::mem_alloc_counter == 0);
212 delete [] dependGraph;
216 template <class Impl>
218 InstQueue<Impl>::name() const
220 return cpu->name() + ".iq";
223 template <class Impl>
225 InstQueue<Impl>::regStats()
228 .name(name() + ".iqInstsAdded")
229 .desc("Number of instructions added to the IQ (excludes non-spec)")
230 .prereq(iqInstsAdded);
233 .name(name() + ".iqNonSpecInstsAdded")
234 .desc("Number of non-speculative instructions added to the IQ")
235 .prereq(iqNonSpecInstsAdded);
240 .name(name() + ".iqIntInstsIssued")
241 .desc("Number of integer instructions issued")
242 .prereq(iqIntInstsIssued);
244 // iqFloatInstsAdded;
247 .name(name() + ".iqFloatInstsIssued")
248 .desc("Number of float instructions issued")
249 .prereq(iqFloatInstsIssued);
251 // iqBranchInstsAdded;
254 .name(name() + ".iqBranchInstsIssued")
255 .desc("Number of branch instructions issued")
256 .prereq(iqBranchInstsIssued);
261 .name(name() + ".iqMemInstsIssued")
262 .desc("Number of memory instructions issued")
263 .prereq(iqMemInstsIssued);
268 .name(name() + ".iqMiscInstsIssued")
269 .desc("Number of miscellaneous instructions issued")
270 .prereq(iqMiscInstsIssued);
272 iqSquashedInstsIssued
273 .name(name() + ".iqSquashedInstsIssued")
274 .desc("Number of squashed instructions issued")
275 .prereq(iqSquashedInstsIssued);
277 iqSquashedInstsExamined
278 .name(name() + ".iqSquashedInstsExamined")
279 .desc("Number of squashed instructions iterated over during squash;"
280 " mainly for profiling")
281 .prereq(iqSquashedInstsExamined);
283 iqSquashedOperandsExamined
284 .name(name() + ".iqSquashedOperandsExamined")
285 .desc("Number of squashed operands that are examined and possibly "
286 "removed from graph")
287 .prereq(iqSquashedOperandsExamined);
289 iqSquashedNonSpecRemoved
290 .name(name() + ".iqSquashedNonSpecRemoved")
291 .desc("Number of squashed non-spec instructions that were removed")
292 .prereq(iqSquashedNonSpecRemoved);
294 for (ThreadID tid = 0; tid < numThreads; tid++) {
295 // Tell mem dependence unit to reg stats as well.
296 memDepUnit[tid].regStats();
301 template <class Impl>
303 InstQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr)
305 DPRINTF(IQ, "Setting active threads list pointer.\n");
306 activeThreads = at_ptr;
309 template <class Impl>
311 InstQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
313 DPRINTF(IQ, "Set the issue to execute queue.\n");
314 issueToExecuteQueue = i2e_ptr;
317 template <class Impl>
319 InstQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
321 DPRINTF(IQ, "Set the time buffer.\n");
324 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
327 template <class Impl>
329 InstQueue<Impl>::entryAmount(ThreadID num_threads)
331 if (iqPolicy == Partitioned) {
332 return numEntries / num_threads;
339 template <class Impl>
341 InstQueue<Impl>::resetEntries()
343 if (iqPolicy != Dynamic || numThreads > 1) {
344 int active_threads = activeThreads->size();
346 std::list<unsigned>::iterator threads = activeThreads->begin();
347 std::list<unsigned>::iterator end = activeThreads->end();
349 while (threads != end) {
350 ThreadID tid = *threads++;
352 if (iqPolicy == Partitioned) {
353 maxEntries[tid] = numEntries / active_threads;
354 } else if (iqPolicy == Threshold && active_threads == 1) {
355 maxEntries[tid] = numEntries;
361 template <class Impl>
363 InstQueue<Impl>::numFreeEntries()
368 template <class Impl>
370 InstQueue<Impl>::numFreeEntries(ThreadID tid)
372 return maxEntries[tid] - count[tid];
375 // Might want to do something more complex if it knows how many instructions
376 // will be issued this cycle.
377 template <class Impl>
379 InstQueue<Impl>::isFull()
381 if (freeEntries == 0) {
388 template <class Impl>
390 InstQueue<Impl>::isFull(ThreadID tid)
392 if (numFreeEntries(tid) == 0) {
399 template <class Impl>
401 InstQueue<Impl>::hasReadyInsts()
404 if (!listOrder.empty()) {
408 for (int i = 0; i < Num_OpClasses; ++i) {
409 if (!readyInsts[i].empty()) {
416 return readyInsts.empty();
419 template <class Impl>
421 InstQueue<Impl>::insert(DynInstPtr &new_inst)
423 // Make sure the instruction is valid
426 DPRINTF(IQ, "Adding instruction PC %#x to the IQ.\n",
429 // Check if there are any free entries. Panic if there are none.
430 // Might want to have this return a fault in the future instead of
432 assert(freeEntries != 0);
434 instList[new_inst->threadNumber].push_back(new_inst);
436 // Decrease the number of free entries.
439 //Mark Instruction as in IQ
440 // new_inst->setInIQ();
442 // Look through its source registers (physical regs), and mark any
444 addToDependents(new_inst);
446 // Have this instruction set itself as the producer of its destination
448 createDependency(new_inst);
450 // If it's a memory instruction, add it to the memory dependency
452 // if (new_inst->isMemRef()) {
453 // memDepUnit[new_inst->threadNumber].insert(new_inst);
455 // If the instruction is ready then add it to the ready list.
456 addIfReady(new_inst);
462 //Update Thread IQ Count
463 count[new_inst->threadNumber]++;
465 assert(freeEntries == (numEntries - countInsts()));
468 template <class Impl>
470 InstQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
472 nonSpecInsts[new_inst->seqNum] = new_inst;
474 // @todo: Clean up this code; can do it by setting inst as unable
475 // to issue, then calling normal insert on the inst.
477 // Make sure the instruction is valid
480 DPRINTF(IQ, "Adding instruction PC %#x to the IQ.\n",
483 // Check if there are any free entries. Panic if there are none.
484 // Might want to have this return a fault in the future instead of
486 assert(freeEntries != 0);
488 instList[new_inst->threadNumber].push_back(new_inst);
490 // Decrease the number of free entries.
493 //Mark Instruction as in IQ
494 // new_inst->setInIQ();
496 // Have this instruction set itself as the producer of its destination
498 createDependency(new_inst);
500 // If it's a memory instruction, add it to the memory dependency
502 if (new_inst->isMemRef()) {
503 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
506 ++iqNonSpecInstsAdded;
508 //Update Thread IQ Count
509 count[new_inst->threadNumber]++;
511 assert(freeEntries == (numEntries - countInsts()));
514 template <class Impl>
516 InstQueue<Impl>::advanceTail(DynInstPtr &inst)
518 // Have this instruction set itself as the producer of its destination
520 createDependency(inst);
523 template <class Impl>
525 InstQueue<Impl>::addToOrderList(OpClass op_class)
527 assert(!readyInsts[op_class].empty());
529 ListOrderEntry queue_entry;
531 queue_entry.queueType = op_class;
533 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
535 ListOrderIt list_it = listOrder.begin();
536 ListOrderIt list_end_it = listOrder.end();
538 while (list_it != list_end_it) {
539 if ((*list_it).oldestInst > queue_entry.oldestInst) {
546 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
547 queueOnList[op_class] = true;
550 template <class Impl>
552 InstQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
554 // Get iterator of next item on the list
555 // Delete the original iterator
556 // Determine if the next item is either the end of the list or younger
557 // than the new instruction. If so, then add in a new iterator right here.
558 // If not, then move along.
559 ListOrderEntry queue_entry;
560 OpClass op_class = (*list_order_it).queueType;
561 ListOrderIt next_it = list_order_it;
565 queue_entry.queueType = op_class;
566 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
568 while (next_it != listOrder.end() &&
569 (*next_it).oldestInst < queue_entry.oldestInst) {
573 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
576 template <class Impl>
578 InstQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
580 // The CPU could have been sleeping until this op completed (*extremely*
581 // long latency op). Wake it if it was. This may be overkill.
584 fuPool->freeUnit(fu_idx);
586 int &size = issueToExecuteQueue->access(0)->size;
588 issueToExecuteQueue->access(0)->insts[size++] = inst;
591 // @todo: Figure out a better way to remove the squashed items from the
592 // lists. Checking the top item of each list to see if it's squashed
593 // wastes time and forces jumps.
594 template <class Impl>
596 InstQueue<Impl>::scheduleReadyInsts()
598 DPRINTF(IQ, "Attempting to schedule ready instructions from "
601 // IssueStruct *i2e_info = issueToExecuteQueue->access(0);
603 // Will need to reorder the list if either a queue is not on the list,
604 // or it has an older instruction than last time.
605 for (int i = 0; i < Num_OpClasses; ++i) {
606 if (!readyInsts[i].empty()) {
607 if (!queueOnList[i]) {
608 addToOrderList(OpClass(i));
609 } else if (readyInsts[i].top()->seqNum <
610 (*readyIt[i]).oldestInst) {
611 listOrder.erase(readyIt[i]);
612 addToOrderList(OpClass(i));
617 // Have iterator to head of the list
618 // While I haven't exceeded bandwidth or reached the end of the list,
619 // Try to get a FU that can do what this op needs.
620 // If successful, change the oldestInst to the new top of the list, put
621 // the queue in the proper place in the list.
622 // Increment the iterator.
623 // This will avoid trying to schedule a certain op class if there are no
624 // FUs that handle it.
625 ListOrderIt order_it = listOrder.begin();
626 ListOrderIt order_end_it = listOrder.end();
627 int total_issued = 0;
628 int exec_queue_slot = i2e_info->size;
630 while (exec_queue_slot < totalWidth && order_it != order_end_it) {
631 OpClass op_class = (*order_it).queueType;
633 assert(!readyInsts[op_class].empty());
635 DynInstPtr issuing_inst = readyInsts[op_class].top();
637 assert(issuing_inst->seqNum == (*order_it).oldestInst);
639 if (issuing_inst->isSquashed()) {
640 readyInsts[op_class].pop();
642 if (!readyInsts[op_class].empty()) {
643 moveToYoungerInst(order_it);
645 readyIt[op_class] = listOrder.end();
646 queueOnList[op_class] = false;
649 listOrder.erase(order_it++);
651 ++iqSquashedInstsIssued;
656 int idx = fuPool->getUnit(op_class);
659 int op_latency = fuPool->getOpLatency(op_class);
661 if (op_latency == 1) {
662 i2e_info->insts[exec_queue_slot++] = issuing_inst;
665 // Add the FU onto the list of FU's to be freed next cycle.
666 fuPool->freeUnit(idx);
668 int issue_latency = fuPool->getIssueLatency(op_class);
670 if (issue_latency > 1) {
671 // Generate completion event for the FU
672 FUCompletion *execution = new FUCompletion(issuing_inst,
675 execution->schedule(curTick() + issue_latency - 1);
677 i2e_info->insts[exec_queue_slot++] = issuing_inst;
680 // Add the FU onto the list of FU's to be freed next cycle.
681 fuPool->freeUnit(idx);
685 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
687 issuing_inst->threadNumber, issuing_inst->readPC(),
688 issuing_inst->seqNum);
690 readyInsts[op_class].pop();
692 if (!readyInsts[op_class].empty()) {
693 moveToYoungerInst(order_it);
695 readyIt[op_class] = listOrder.end();
696 queueOnList[op_class] = false;
699 issuing_inst->setIssued();
702 if (!issuing_inst->isMemRef()) {
703 // Memory instructions can not be freed from the IQ until they
706 count[issuing_inst->threadNumber]--;
707 issuing_inst->removeInIQ();
709 memDepUnit[issuing_inst->threadNumber].issue(issuing_inst);
712 listOrder.erase(order_it++);
719 cpu->activityThisCycle();
721 DPRINTF(IQ, "Not able to schedule any instructions.\n");
726 template <class Impl>
728 InstQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
730 DPRINTF(IQ, "Marking nonspeculative instruction with sequence "
731 "number %i as ready to execute.\n", inst);
733 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
735 assert(inst_it != nonSpecInsts.end());
737 // ThreadID tid = (*inst_it).second->threadNumber;
739 // Mark this instruction as ready to issue.
740 (*inst_it).second->setCanIssue();
742 // Now schedule the instruction.
743 // if (!(*inst_it).second->isMemRef()) {
744 addIfReady((*inst_it).second);
746 // memDepUnit[tid].nonSpecInstReady((*inst_it).second);
749 nonSpecInsts.erase(inst_it);
752 template <class Impl>
754 InstQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
756 /*Need to go through each thread??*/
757 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
760 ListIt iq_it = instList[tid].begin();
762 while (iq_it != instList[tid].end() &&
763 (*iq_it)->seqNum <= inst) {
765 instList[tid].pop_front();
768 assert(freeEntries == (numEntries - countInsts()));
771 template <class Impl>
773 InstQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
775 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
776 // Look at the physical destination register of the DynInst
777 // and look it up on the dependency graph. Then mark as ready
778 // any instructions within the instruction queue.
780 DependencyEntry *curr;
781 DependencyEntry *prev;
783 // Tell the memory dependence unit to wake any dependents on this
784 // instruction if it is a memory instruction. Also complete the memory
785 // instruction at this point since we know it executed fine.
786 // @todo: Might want to rename "completeMemInst" to
787 // something that indicates that it won't need to be replayed, and call
788 // this earlier. Might not be a big deal.
789 if (completed_inst->isMemRef()) {
790 // memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
791 completeMemInst(completed_inst);
793 completed_inst->wakeDependents();
795 for (int dest_reg_idx = 0;
796 dest_reg_idx < completed_inst->numDestRegs();
799 PhysRegIndex dest_reg =
800 completed_inst->renamedDestRegIdx(dest_reg_idx);
802 // Special case of uniq or control registers. They are not
803 // handled by the IQ and thus have no dependency graph entry.
804 // @todo Figure out a cleaner way to handle this.
805 if (dest_reg >= numPhysRegs) {
809 DPRINTF(IQ, "Waking any dependents on register %i.\n",
812 //Maybe abstract this part into a function.
813 //Go through the dependency chain, marking the registers as ready
814 //within the waiting instructions.
816 curr = dependGraph[dest_reg].next;
819 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
820 curr->inst->readPC());
822 // Might want to give more information to the instruction
823 // so that it knows which of its source registers is ready.
824 // However that would mean that the dependency graph entries
825 // would need to hold the src_reg_idx.
826 curr->inst->markSrcRegReady();
828 addIfReady(curr->inst);
830 DependencyEntry::mem_alloc_counter--;
839 // Reset the head node now that all of its dependents have been woken
841 dependGraph[dest_reg].next = NULL;
842 dependGraph[dest_reg].inst = NULL;
844 // Mark the scoreboard as having that register ready.
845 regScoreboard[dest_reg] = true;
850 template <class Impl>
852 InstQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
854 // OpClass op_class = ready_inst->opClass();
856 readyInsts.push(ready_inst);
858 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
859 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
860 ready_inst->readPC(), ready_inst->opClass(), ready_inst->seqNum);
863 template <class Impl>
865 InstQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
867 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
870 template <class Impl>
872 InstQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
874 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
877 template <class Impl>
879 InstQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
881 ThreadID tid = completed_inst->threadNumber;
883 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
884 completed_inst->readPC(), completed_inst->seqNum);
888 // completed_inst->memOpDone = true;
890 // memDepUnit[tid].completed(completed_inst);
895 template <class Impl>
897 InstQueue<Impl>::violation(DynInstPtr &store,
898 DynInstPtr &faulting_load)
900 memDepUnit[store->threadNumber].violation(store, faulting_load);
903 template <class Impl>
905 InstQueue<Impl>::squash(ThreadID tid)
907 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
910 // Read instruction sequence number of last instruction out of the
912 // squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
914 // Setup the squash iterator to point to the tail.
915 squashIt[tid] = instList[tid].end();
918 // Call doSquash if there are insts in the IQ
919 if (count[tid] > 0) {
923 // Also tell the memory dependence unit to squash.
924 // memDepUnit[tid].squash(squashedSeqNum[tid], tid);
927 template <class Impl>
929 InstQueue<Impl>::doSquash(ThreadID tid)
931 // Make sure the squashed sequence number is valid.
932 assert(squashedSeqNum[tid] != 0);
934 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
935 tid, squashedSeqNum[tid]);
937 // Squash any instructions younger than the squashed sequence number
939 while (squashIt[tid] != instList[tid].end() &&
940 (*squashIt[tid])->seqNum > squashedSeqNum[tid]) {
942 DynInstPtr squashed_inst = (*squashIt[tid]);
944 // Only handle the instruction if it actually is in the IQ and
945 // hasn't already been squashed in the IQ.
946 if (squashed_inst->threadNumber != tid ||
947 squashed_inst->isSquashedInIQ()) {
952 if (!squashed_inst->isIssued() ||
953 (squashed_inst->isMemRef()/* &&
954 !squashed_inst->memOpDone*/)) {
956 // Remove the instruction from the dependency list.
957 if (!squashed_inst->isNonSpeculative()) {
959 for (int src_reg_idx = 0;
960 src_reg_idx < squashed_inst->numSrcRegs();
963 PhysRegIndex src_reg =
964 squashed_inst->renamedSrcRegIdx(src_reg_idx);
966 // Only remove it from the dependency graph if it was
967 // placed there in the first place.
968 // HACK: This assumes that instructions woken up from the
969 // dependency chain aren't informed that a specific src
970 // register has become ready. This may not always be true
972 // Instead of doing a linked list traversal, we can just
973 // remove these squashed instructions either at issue time,
974 // or when the register is overwritten. The only downside
975 // to this is it leaves more room for error.
977 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
978 src_reg < numPhysRegs) {
979 dependGraph[src_reg].remove(squashed_inst);
983 ++iqSquashedOperandsExamined;
986 // Might want to remove producers as well.
988 nonSpecInsts[squashed_inst->seqNum] = NULL;
990 nonSpecInsts.erase(squashed_inst->seqNum);
992 ++iqSquashedNonSpecRemoved;
995 // Might want to also clear out the head of the dependency graph.
997 // Mark it as squashed within the IQ.
998 squashed_inst->setSquashedInIQ();
1000 // @todo: Remove this hack where several statuses are set so the
1001 // inst will flow through the rest of the pipeline.
1002 squashed_inst->setIssued();
1003 squashed_inst->setCanCommit();
1004 // squashed_inst->removeInIQ();
1006 //Update Thread IQ Count
1007 count[squashed_inst->threadNumber]--;
1011 if (numThreads > 1) {
1012 DPRINTF(IQ, "[tid:%i]: Instruction PC %#x squashed.\n",
1013 tid, squashed_inst->readPC());
1015 DPRINTF(IQ, "Instruction PC %#x squashed.\n",
1016 squashed_inst->readPC());
1021 ++iqSquashedInstsExamined;
1025 template <class Impl>
1027 InstQueue<Impl>::DependencyEntry::insert(DynInstPtr &new_inst)
1029 //Add this new, dependent instruction at the head of the dependency
1032 // First create the entry that will be added to the head of the
1033 // dependency chain.
1034 DependencyEntry *new_entry = new DependencyEntry;
1035 new_entry->next = this->next;
1036 new_entry->inst = new_inst;
1038 // Then actually add it to the chain.
1039 this->next = new_entry;
1041 ++mem_alloc_counter;
1044 template <class Impl>
1046 InstQueue<Impl>::DependencyEntry::remove(DynInstPtr &inst_to_remove)
1048 DependencyEntry *prev = this;
1049 DependencyEntry *curr = this->next;
1051 // Make sure curr isn't NULL. Because this instruction is being
1052 // removed from a dependency list, it must have been placed there at
1053 // an earlier time. The dependency chain should not be empty,
1054 // unless the instruction dependent upon it is already ready.
1059 // Find the instruction to remove within the dependency linked list.
1060 while (curr->inst != inst_to_remove) {
1064 assert(curr != NULL);
1067 // Now remove this instruction from the list.
1068 prev->next = curr->next;
1070 --mem_alloc_counter;
1072 // Could push this off to the destructor of DependencyEntry
1078 template <class Impl>
1080 InstQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1082 // Loop through the instruction's source registers, adding
1083 // them to the dependency list if they are not ready.
1084 int8_t total_src_regs = new_inst->numSrcRegs();
1085 bool return_val = false;
1087 for (int src_reg_idx = 0;
1088 src_reg_idx < total_src_regs;
1091 // Only add it to the dependency graph if it's not ready.
1092 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1093 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1095 // Check the IQ's scoreboard to make sure the register
1096 // hasn't become ready while the instruction was in flight
1097 // between stages. Only if it really isn't ready should
1098 // it be added to the dependency graph.
1099 if (src_reg >= numPhysRegs) {
1101 } else if (regScoreboard[src_reg] == false) {
1102 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1103 "is being added to the dependency chain.\n",
1104 new_inst->readPC(), src_reg);
1106 dependGraph[src_reg].insert(new_inst);
1108 // Change the return value to indicate that something
1109 // was added to the dependency graph.
1112 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1113 "became ready before it reached the IQ.\n",
1114 new_inst->readPC(), src_reg);
1115 // Mark a register ready within the instruction.
1116 new_inst->markSrcRegReady();
1124 template <class Impl>
1126 InstQueue<Impl>::createDependency(DynInstPtr &new_inst)
1128 //Actually nothing really needs to be marked when an
1129 //instruction becomes the producer of a register's value,
1130 //but for convenience a ptr to the producing instruction will
1131 //be placed in the head node of the dependency links.
1132 int8_t total_dest_regs = new_inst->numDestRegs();
1134 for (int dest_reg_idx = 0;
1135 dest_reg_idx < total_dest_regs;
1138 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1140 // Instructions that use the misc regs will have a reg number
1141 // higher than the normal physical registers. In this case these
1142 // registers are not renamed, and there is no need to track
1143 // dependencies as these instructions must be executed at commit.
1144 if (dest_reg >= numPhysRegs) {
1148 if (dependGraph[dest_reg].next) {
1150 panic("Dependency graph %i not empty!", dest_reg);
1153 dependGraph[dest_reg].inst = new_inst;
1155 // Mark the scoreboard to say it's not yet ready.
1156 regScoreboard[dest_reg] = false;
1160 template <class Impl>
1162 InstQueue<Impl>::addIfReady(DynInstPtr &inst)
1164 //If the instruction now has all of its source registers
1165 // available, then add it to the list of ready instructions.
1166 if (inst->readyToIssue()) {
1168 //Add the instruction to the proper ready list.
1169 if (inst->isMemRef()) {
1171 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1173 // Message to the mem dependence unit that this instruction has
1174 // its registers ready.
1176 // memDepUnit[inst->threadNumber].regsReady(inst);
1181 // OpClass op_class = inst->opClass();
1183 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1184 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
1185 inst->readPC(), inst->opClass(), inst->seqNum);
1187 readyInsts.push(inst);
1191 template <class Impl>
1193 InstQueue<Impl>::countInsts()
1195 //ksewell:This works but definitely could use a cleaner write
1196 //with a more intuitive way of counting. Right now it's
1197 //just brute force ....
1200 int total_insts = 0;
1202 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1203 ListIt count_it = instList[tid].begin();
1205 while (count_it != instList[tid].end()) {
1206 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1207 if (!(*count_it)->isIssued()) {
1209 } else if ((*count_it)->isMemRef() &&
1210 !(*count_it)->memOpDone) {
1211 // Loads that have not been marked as executed still count
1212 // towards the total instructions.
1223 return numEntries - freeEntries;
1227 template <class Impl>
1229 InstQueue<Impl>::dumpDependGraph()
1231 DependencyEntry *curr;
1233 for (int i = 0; i < numPhysRegs; ++i)
1235 curr = &dependGraph[i];
1238 cprintf("dependGraph[%i]: producer: %#x [sn:%lli] consumer: ",
1239 i, curr->inst->readPC(), curr->inst->seqNum);
1241 cprintf("dependGraph[%i]: No producer. consumer: ", i);
1244 while (curr->next != NULL) {
1247 cprintf("%#x [sn:%lli] ",
1248 curr->inst->readPC(), curr->inst->seqNum);
1255 template <class Impl>
1257 InstQueue<Impl>::dumpLists()
1259 for (int i = 0; i < Num_OpClasses; ++i) {
1260 cprintf("Ready list %i size: %i\n", i, readyInsts.size());
1265 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1267 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1268 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1270 cprintf("Non speculative list: ");
1272 while (non_spec_it != non_spec_end_it) {
1273 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
1274 (*non_spec_it).second->seqNum);
1280 ListOrderIt list_order_it = listOrder.begin();
1281 ListOrderIt list_order_end_it = listOrder.end();
1284 cprintf("List order: ");
1286 while (list_order_it != list_order_end_it) {
1287 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1288 (*list_order_it).oldestInst);
1298 template <class Impl>
1300 InstQueue<Impl>::dumpInsts()
1302 for (ThreadID tid = 0; tid < numThreads; ++tid) {
1304 // int valid_num = 0;
1306 ListIt inst_list_it = instList[tid].begin();
1308 while (inst_list_it != instList[tid].end())
1310 cprintf("Instruction:%i\n",
1312 if (!(*inst_list_it)->isSquashed()) {
1313 if (!(*inst_list_it)->isIssued()) {
1315 cprintf("Count:%i\n", valid_num);
1316 } else if ((*inst_list_it)->isMemRef() &&
1317 !(*inst_list_it)->memOpDone) {
1318 // Loads that have not been marked as executed still count
1319 // towards the total instructions.
1321 cprintf("Count:%i\n", valid_num);
1325 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1326 "Issued:%i\nSquashed:%i\n",
1327 (*inst_list_it)->readPC(),
1328 (*inst_list_it)->seqNum,
1329 (*inst_list_it)->threadNumber,
1330 (*inst_list_it)->isIssued(),
1331 (*inst_list_it)->isSquashed());
1333 if ((*inst_list_it)->isMemRef()) {
1334 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);